All the earlier prototypes are good stuff, but does the idea scale? Although this Oak and Aspen box is physically even smaller than the first two 4 PE TTL_PAPERS boxes, it was put together for the sole purpose of demonstrating that the design scales at least to an 8 PE cluster. We were not very particular about how it would prove scalability, so the functionality is essentially a supercharged version of what TTL_PAPERS supports, with the state machine timing properties of PAPERS1. Thus, it provides static barrier synchronization with 4-bit NANDing, all done with 2 cycle speed. Inside the box....
The single wire-wrapped circuit board is very densely packed with a variety of TTL and AMD PAL parts implementing a non-partitionable static barrier mechanism. Unfortunately, the wire-wrap was apparently a bit too dense, because we measured something on the order of a 2 volt spike on one wire that wasn't supposed to be doing anything at the time... a few capacitors cleared-up these little problems, but left us cursing wire-wrap. We also used a different method to connect the cables to the board: we made a little DIP header for each group of similar signals from the PCs. We will not do that again either. Oh yeah. It also was the first PAPERS unit to need a heat sink on its 7805 and a fan.
Ok, so this one was mostly an evolutionary dead end. Anyway, it works and it is fun to watch the 8 bi-color LEDs as it plays one of our MIMD multi-voice music demos.
The only thing set in stone is our name.