EE380 Assignment 2

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1. 100%, A particular program expressed in a particular ISA executes 100 ALU instructions, 10 Loads, 8 Stores, and 2 Branches. A simple, non-pipelined, implementation of that ISA takes 7 CPI for each ALU instruction, 20 CPI for each load, 10 CPI for each Store, and 10 CPI for each Branch. The original clock frequency is 200MHz. How many clock cycles would the program take to execute? How many nanoseconds would the program take to execute?
   
2. 100%, Given the circumstances described in question 1 above, which of the following three changes would yield at least 2X speedup?
   An improved memory design reduces the CPI for load from 20 to 10
   A new compiler reduces the number of ALU instructions from 100 to 50
   New VLSI fabrication technology changes the clock period to 4ns
   Any of the above three would suffice to give at least 2X speedup
   None of the above three would suffice to give at least 2X speedup
3. 100%, Synthetic benchmarks are very popular, but often do not end-up being a very good predictor of performance on the actual application they were intended to model. Do they tend to underestimate or overestimate performance? Why?
   
4. 100% Given this processor hardware design and the control sequence below, describe in words (or C-like pseudo code) the function of the instruction xyzzy rs,immed(rt).

   when op(0x3f) op(1) Xyzzy
   
   Start:
    PCout, MARin, MEMread, Yin
    CONST(4), ALUadd, Zin, UNTILmfc
    MDRout, IRin
    Zout, PCin, JUMPonop
    HALT /* Should end here on undecoded op */
   
   Xyzzy:
    SELrt, REGout, Yin
    IRimmedout, ALUadd, Zin
    Zout, MARin, MEMread
    SELrs, REGout, Yin, UNTILmfc
    MDRout, SELrs, REGin
    Yout, MDRin, MEMwrite, JUMP(Start)
   

   
   
5. 100% Given the xyzzy rs,immed(rt) instruction as defined above, and assuming that a memory load request takes 3 clock cycles to complete (after MEMread has been issued), how many CPI would each xyzzy instruction require? You may use the simulator to get or check your answer. In any case, give and briefly explain your answer here:
   
6. 100% Given this processor hardware design, suppose that the following control state is the limiting factor in determining the maximum clock speed. Given that the propagation delay associated with SELrs is 8ns, REGout is 2ns, MDRin is 4ns, ALUadd is 16ns, and Zin is 4ns, what is the period (in nanoseconds) of the fastest allowable clock? You may use the simulator to get or check your answer. In any case, give and briefly explain your answer here:

   SELrs, REGout, MDRin, ALUadd, Zin
   

   
   
7. 100%, A particular program consists of two functions, a() and b(). Initially, a() takes 900 clock cycles and b() takes 100 clock cycles. What is the maximum possible overall speedup that could be obtained by making changes that only affect the execution speed of a()?
   

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