An 8-bit 2's-complement number can hold any value from -128 to 127. That means adding two such values can result in a value from -256 to 254... and many of those possible result values do not fit in 8 bits. Let's take a particular example. What is 127 + 1? Well, recall that a 2's complement adder has the wonderful property that it is exactly the same circuit as an unsigned adder. Thus: 8'b01111111 + 8'b00000001 is 8'b10000000. The bad news is that 8'b10000000 is the bit pattern that represents -128. This unfortunate wrap-around of values can cause serious problems for "natural data types" -- values representing analog voltages, etc.
The fix is pretty simple. Conventional computer arithmetic is technically known as modular arithmetic: the result for an out-of-range value is simply the low bits of the correct value. What we need instead is saturation arithmetic: the result for an out-of-range value is the limit value in that direction. For signed 8-bit numbers, that means -128 for the low and 127 for the high. Here's a little Verilog program to compute the signed saturation values for adding two 8-bit numbers:
module refsatadd8; reg signed [7:0] a, b, s; reg signed [8:0] t; initial begin a=0; repeat (256) begin b=0; repeat (256) begin t = a + b; // 9-bit result if (t < -128) s = -128; // signed less than else if (t > 127) s = 127; // signed greater than else s = t[7:0]; $display("%d\t%d\t%d", a, b, s); b=b+1; end a=a+1; end end endmodule
Well, that was easy! Yeah, but that's not what I want you to do. I want you to design a synthesizable, combinatorial logic, 8-bit signed saturation adder without using the Verilog + operator (or anything else that automatically builds the adder for you). Feel free to build a ripple carry or whatever seems easiest. I'll also give you the hint that the ordinary add result only and always goes out of range when both operands have the same sign and the result has the opposite sign. You know the sign; it's bit 7.
Your project is simply to write two things in Verilog:
$display("All cases tested; %d correct, %d failed", correct, failed);
Place all your verilog code for the above in one file called satadd8.v. That's the file you need to submit.
Naturally, I also expect you to run that file through a Verilog compiler:
iverilog -o satadd8 satadd8.v
And to run the simulation to test it:
Which will hopefully result in it printing just:
All cases tested; 65536 correct, 0 failed
If not, and you can't figure-out how to fix it, as Ricky Ricardo would say, you got some splainin to do. ;-)
You should be submitting an implementor's notes document with your project. Just a couple of quick comments about that....
Your implementor's notes certainly should describe the logic used to implement your satadd8 module. That can be done as text. I am not requiring you to provide a schematic of your satadd8 module... but practice creating schematics is certainly a good thing (i.e., a skill you will need in this course) and it wouldn't hurt to include a schematic.
Although I would encourage you to think about generating a VCD file and using gtkwave to visualize it, I don't think there's much point in doing that for a simple combinatorial circuit like satadd8. If you do find it useful, you may include a screen grab from gtkwave in your implementor's notes.
The recommended due date for this assignment is before class, Friday, February 12, 2016. This submission window will close when class begins on Feb 19, 2016. You may submit as many times as you wish, but only the last submission that you make before class begins on Feb. 19, 2016 will be counted toward your course grade. Due to server out-of-space errors, some of you had submissions return errors. Submissions will thus be accepted up to class time on Monday, Feb. 22.
Note that you can ensure that you get at least half credit for this project by simply submitting a tar of an "implementor's notes" document explaining that your project doesn't work because you have not done it yet. Given that, perhaps you should start by immediately making and submitting your implementor's notes document? (I would!)
For each project, you will be submitting a tarball (i.e., a file with the name ending in .tar or .tgz) that contains all things relevant to your work on the project. Minimally, each project tarball includes the source code for the project and a semi-formal "implementors notes" document as a PDF named notes.pdf. It also may include test cases, sample output, a make file, etc., but should not include any files that are built by your Makefile (e.g., no binary executables). For this particular project, name the Verilog source file satadd8.v.
Submit your tarball below. The file can be either an ordinary .tar file created using tar cvf file.tar yourprojectfiles or a compressed .tgz file file created using tar zcvf file.tgz yourprojectfiles. Be careful about using * as a shorthand in listing yourprojectfiles on the command line, because if the output tar file is listed in the expansion, the result can be an infinite file (which is not ok).