# Assignment 0: Maximum Of Two 8-Bit Unsigned Binary Integers

Return the maximum of two unsigned binary integers? How hard can that be? Well, it's actually easier than you think, but not for the reason you think it would be easy.

The normal way to think about computing the maximum of two values is to do a comparison. Here's a little Verilog program to compute the maximum of all possible pairs of 8-bit unsigned binary integers:

```module demomax;
reg [7:0] a, b, m;
initial begin
a=0;
repeat (256) begin
b=0;
repeat (256) begin
if (a > b) m=a; else m=b;
\$display("%d\t%d\t%d", a, b, m);
b=b+1;
end
a=a+1;
end
end
endmodule
```

Well, that was easy! Yeah, but what hardware do you think would be generated by the > operator? The unfortunate answer is that it probably uses an entire ALU to implement a subtract and then essentially checks to see if the result was negative. However, maximum can be efficiently implemented with less circuitry.

The maximum of two values is always identical to one of them -- we just need to figure out which one. Initially, we don't know which value is the maximum. Begin by comparing the two MSB (most significant bit) bits. If they are different, the value with a 1 in that position is the maximum. If the bits match, then we need to examine the next bit lower position... and so the process continues until differing bits are found or we've processed the LSB (least significant bit). If no bits were different, the values are identical and you'll get the maximum value no matter which of the two values you pick.

Not comfortable with that algorithm? OK. You can also do this by essentially building a subtract circuit that doesn't compute a result -- it just computes the carry out. Recall that a-b is the same as a+((~b)+1). Well, without actually computing the sum, you know b>a if a-b is negative, which you can tell by simply looking at the final carry out. A final carry out of 1 means b is the maximum, otherwise, use a.

I want you to design a synthesizable, combinatorial logic, 8-bit unsigned maximum circuit without using any of the Verilog word-level operators to determine which value is the maximum -- you cannot use >, -, +, etc. In fact, to be even more annoying, I also forbid you from using the >> or other word-level operators to extract bits: use only vector subscripting. That said, you are free to use any bit-level algorithm you wish for your synthesizable, purely combinatorial, circuit design.

Your project is about writing a Verilog module called max, but there are actually two other chunks of Verilog code you need in order to test it. The three required modules of Verilog code are:

1. The definition of a module that starts with module refmax(s, a, b); and implements an unsigned maximum of 8-bit values a and b to give the 8-bit result m. This module should be derived from the code for demomax above. It MUST use Verilog's > operator and doesn't need to be synthesizable. This is to be as straightforward an implementation as possible; it will serve as your oracle to deliver known correct answers.
2. The definition of a module that starts with module max(m, a, b); and implements an unsigned maximum of 8-bit values a and b to give the 8-bit result m. Of course, it may instantiate other combinatorial logic modules to implement its functionality, e.g., you might start with defining a one-bit comparison module and instantiate copies of it within the definition of max. However, this module MUST be synthesizable, purely combinatorial, logic and it is not permitted to use the Verilog > operator, nor other operators as described above, in itself nor in anything it instantiates.
3. The definition of a non-synthesizable module that starts with module testbench; and instantiates a max which it exhaustively tests for correctness. Note that it is not sufficient to just print what happens for all 65,536 possible combinations of inputs; I don't want just a stimulus module. Who would want to manually check 65,536 lines of output? Your testbench must not only try each possible input combination, but also must check that the answer from your max matches the answer from refmax in each case. Your testbench should only output the combinations of inputs for which the answer from max was wrong. Further, it should count how many input combinations were correct and how many failed. The last line of text output should be generated by Verilog code like:
```\$display("All cases tested; %d correct, %d failed", correct, failed);
```

Place all your verilog code for the above in one file called max.v. That's the file you need to submit.

Naturally, I also expect you to run that file through a Verilog compiler either using our CGI interface or Icarus Verilog directly:

```iverilog -o max max.v
```

And to run the simulation to test it:

```vvp max
```

Which will hopefully result in it printing just:

```All cases tested; 65536 correct, 0 failed
```

If not, and you can't figure-out how to fix it, as Ricky Ricardo would say, you got some splainin to do. ;-)

## Details For The Implementor's Notes

You should be submitting an implementor's notes document with your project. Just a couple of quick comments about that....

Your implementor's notes certainly should describe the logic used to implement your max module. That can be done as text. I am not requiring you to provide a schematic of your max module... but practice creating schematics is certainly a good thing (i.e., a skill you will need in this course) and it wouldn't hurt to include a schematic.

Although I would encourage you to think about generating a VCD file and using gtkwave to visualize it, I don't think there's much point in doing that for a simple combinatorial circuit like max. If you do find it useful, you may include a screen grab from gtkwave in your implementor's notes.

## Due Dates

The recommended due date for this assignment is before class, Monday, September 11, 2017. This submission window will close when class begins on Wednesday, September 13, 2017. You may submit as many times as you wish, but only the last submission that you make before class begins on Wednesday, September 13, 2017 will be counted toward your course grade.

Note that you can ensure that you get at least half credit for this project by simply submitting a tar of an "implementor's notes" document explaining that your project doesn't work because you have not done it yet. Given that, perhaps you should start by immediately making and submitting your implementor's notes document? (I would!)

## Submission Procedure

For each project, you will be submitting a tarball (i.e., a file with the name ending in .tar or .tgz) that contains all things relevant to your work on the project. Minimally, each project tarball includes the source code for the project and a semi-formal "implementors notes" document as a PDF named notes.pdf. It also may include test cases, sample output, a make file, etc., but should not include any files that are built by your Makefile (e.g., no binary executables). For this particular project, name the Verilog source file max.v.

Submit your tarball below. The file can be either an ordinary .tar file created using tar cvf file.tar yourprojectfiles or a compressed .tgz file file created using tar zcvf file.tgz yourprojectfiles. Be careful about using * as a shorthand in listing yourprojectfiles on the command line, because if the output tar file is listed in the expansion, the result can be an infinite file (which is not ok).