Assignment 4: E Pluribus Unum?

Out of many, one. This project is the SIMD parallel pipelined Verilog implementation of the KySMet instruction set architecture. You are going to make it parametric such that any reasonable number of PEs (processing elements) can be built. Your Verilog code should have one `define parameter, `NPROC, which you can change to change the total number of PEs.

Where To Start?

Well, naturally you'll start with the previous project's solution. Sort-of. Actually, you should start with something like this:

You already know how to pipeline the processor. Now begin by thinking about the overall structure for parallelizing the CU (control unit) and PEs (processing elements).

As you start to partition the pipelined design across the CU and PEs, think carefully about which aspects of each instruction are done where. For example, a jump instruction really doesn't do anything in the PEs.

Due Dates

The recommended due date is Monday, April 23, 2018 (the start of dead week). By that time, you should definitely have at least submitted something that includes the assembler specification (kysmet.aik), and Implementor's Notes including an overview of the structure of your intended design. That overview could be in the form of a diagram, or it could be a list of top-level modules, but it is important in that it ensures you are on the right track. Final submissions will be accepted up to just before the final exam on Tuesday, May 1, 2018 (at 3:30PM, if you really want to cut it close).

Submission Procedure

For each project, you will be submitting a tarball (i.e., a file with the name ending in .tar or .tgz) that contains all things relevant to your work on the project. Minimally, each project tarball includes the source code for the project and a semi-formal "implementors notes" document as a PDF named notes.pdf. It also may include test cases, sample output, a make file, etc., but should not include any files that are built by your Makefile (e.g., no binary executables). Be sure to make it obvious which files are which; for example, if the Verilog source file isn't kysmet.v or the AIK file isn't kysmet.aik, you should be saying where these things are in your implementor's notes.

Submit your tarball below. The file can be either an ordinary .tar file created using tar cvf file.tar yourprojectfiles or a compressed .tgz file file created using tar zcvf file.tgz yourprojectfiles. Be careful about using * as a shorthand in listing yourprojectfiles on the command line, because if the output tar file is listed in the expansion, the result can be an infinite file (which is not ok).

Your team name is .
Your password is


EE480 Advanced Computer Architecture.