Sample Encoding of SIMD MIPS Assembler

Here are two alternative versions of the AIK specification for the SIMD MIPS project.

The First Version

The following is the AIK code for the sample solution.

Sample AIK Assembler Specification

Sample Assembly Language Input

An Alternative...

Here's another way to do this... listing a separate line for each assembly instruction. It's verbose, but obvious.

Sample AIK Assembler Specification

addu8	$rd,$rs,$rt	:=	0:6 rs:5 rt:5 rd:5 0:5 32:6
addu	$rd,$rs,$rt	:=	0:6 rs:5 rt:5 rd:5 0:5 33:6
subu	$rd,$rs,$rt	:=	0:6 rs:5 rt:5 rd:5 0:5 35:6
and	$rd,$rs,$rt	:=	0:6 rs:5 rt:5 rd:5 0:5 36:6
or	$rd,$rs,$rt	:=	0:6 rs:5 rt:5 rd:5 0:5 37:6
xor	$rd,$rs,$rt	:=	0:6 rs:5 rt:5 rd:5 0:5 38:6
sltu	$rd,$rs,$rt	:=	0:6 rs:5 rt:5 rd:5 0:5 43:6

addiu	$rt,$rs,imm	:=	9:6 rs:5 rt:5 imm:16
sltiu	$rt,$rs,imm	:=	11:6 rs:5 rt:5 imm:16
andi	$rt,$rs,imm	:=	12:6 rs:5 rt:5 imm:16
ori	$rt,$rs,imm	:=	13:6 rs:5 rt:5 imm:16
xori	$rt,$rs,imm	:=	14:6 rs:5 rt:5 imm:16
lui	$rt,imm		:=	15:6 0:5 rt:5 imm:16

beq	$rs,$rt,lab	:=	4:6 rs:5 rt:5 ((lab-(.+4))/4):16

lw	$rt,imm[$rs]	:=	35:6 rs:5 rt:5 imm:16
sw	$rt,imm[$rs]	:=	43:6 rs:5 rt:5 imm:16

paddu8	$rd,$rs,$rt	:=	16:6 rs:5 rt:5 rd:5 0:5 32:6
paddu	$rd,$rs,$rt	:=	16:6 rs:5 rt:5 rd:5 0:5 33:6
psubu	$rd,$rs,$rt	:=	16:6 rs:5 rt:5 rd:5 0:5 35:6
pand	$rd,$rs,$rt	:=	16:6 rs:5 rt:5 rd:5 0:5 36:6
por	$rd,$rs,$rt	:=	16:6 rs:5 rt:5 rd:5 0:5 37:6
pxor	$rd,$rs,$rt	:=	16:6 rs:5 rt:5 rd:5 0:5 38:6
psltu	$rd,$rs,$rt	:=	16:6 rs:5 rt:5 rd:5 0:5 43:6
plui	$rt,imm		:=	31:6 0:5 rt:5 imm:16

paddiu	$rt,$rs,imm	:=	25:6 rs:5 rt:5 imm:16
psltiu	$rt,$rs,imm	:=	27:6 rs:5 rt:5 imm:16
pandi	$rt,$rs,imm	:=	28:6 rs:5 rt:5 imm:16
pori	$rt,$rs,imm	:=	29:6 rs:5 rt:5 imm:16
pxori	$rt,$rs,imm	:=	30:6 rs:5 rt:5 imm:16

offeq	$rs,$rt		:=	16:6 rs:5 rt:5 0:5 0:5 0:6
pushen			:=	16:6 rs:5 rt:5 rd:5 0:5 4:6
popen			:=	16:6 rs:5 rt:5 rd:5 0:5 5:6

gor	$rs,$rt		:=	16:6 rs:5 rt:5 0:5 0:5 1:6
bcast	$rs,$rt		:=	16:6 rs:5 rt:5 0:5 0:5 2:6
net	$rd,$rs,$rt	:=	16:6 rs:5 rt:5 rd:5 0:5 34:6

.const { zero 2 v0 v1 a0 a1 a2 a3 t0 t1 t2 t3 t4 t5 t6 t7
         s0 s1 s2 s3 s4 s5 s6 s7 t8 t9 28 gp sp fp ra
         28 live iproc nproc ac }
.segment .text 8 0x10000 0 .VMEM
.segment .data 8 0x10000 0 .VMEM

Sample Assembly Language Input

Advanced Computer Architecture.