We are in the process of reworking this site to incorporate the information that was formerly at Purdue University. We thank you for your patience.
SWAR (SIMD Within A Register) is a processing model which applies SIMD parallel processing across sections of a CPU register. It is a vector model, which places no restrictions on the length of the vectors or the precision of the data in the vectors. (If you've got 3-bit data, why shouldn't you be able to pack 21 items in a 64-bit register?)
There are many SWAR instruction sets that were designed for multimedia processing, including MMX, 3DNow!, SSE, and AltiVec. In fact, the SWAR model has its roots in a compilers class project for targetting MMX. However, the SWAR processing model is not limited to these multimedia architectures. It is generally applicable to any architecture in which registers and/or datapath are divided into parallelized fields (for example, some GPU or microcontroller systems). It can even be applied to systems which have no direct support for it at all (for example, a pre-MMX Pentium system).
The acronym "SWAR" was coined by Hank Dietz and Randy Fisher one day in Hank's office in the MSEE building at Purdue University. Since then, it has become a part of the lexicon (See http://en.wikipedia.org/wiki/SWAR), although we usually don't get any credit for it.
Information on the SWARC parallel programming language can be found here.
Information on the Scc experimental SWARC compiler can be found here.
All other SWAR support code, the SWARC compiler, etc., was formerly hosted at the old SWAR home, http://shay.ecn.purdue.edu/~swar/. We are in the process of moving the materials still at the Purdue site to the main aggregate.org site, which is hosted by the University of Kentucky.
Randy's doctoral thesis, which describes the SWAR model, is available here in PostScript and Portable Document Format.
The MMX/3DNow! macros discussed in the Ars Technica article on KLAT2 are available as the GCC header file ars-swar.h.
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