EE380 Assignment 1

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  1. 100% Here's something you know from EE280: Which of the following logic equations implements a multiplexor with two inputs, i0 and i1, and one select line, s?
    ((s OR (NOT i0)) AND (s OR i1))
    ((s AND (NOT i0)) OR (s AND i1))
    ((s AND (NOT i1)) OR (s AND i0))
    ((i0 AND (NOT s)) OR (i1 AND s))
    ((i1 AND (NOT s)) OR (i0 AND s))
  2. 100% Which of the following four statements is false?
    Registers often are built using D flip-flops.
    A one-bit SRAM cell is physically smaller than a one-bit DRAM cell.
    A multiplexor can be implemented using a decoder and tri-state drivers.
    Open-collector logic is the prefered method used to ensure that only one of multiple outputs connected to the same bus wire is active at any point in time.
    None of the above is false.
  3. 100% Given this processor hardware design, add control states to the following to implement a bitwise AND instruction (as decoded by the when below), such that and rd,rs,rt yields rd=(rs AND rt). You should add initial values and test your design using the simulator before submitting it here.
  4. 100% Given this processor hardware design, add control states to the following to implement a memory AND instruction (as decoded by the when below), such that Mand rs,immed(rt) yields memory[rt + immed] = (rs & memory[rt + immed]). Note that the code given below already implements MIPS "load word" and "store word" instructions... your control logic should work like load, AND the value from register rs, and store the result. You should add initial values and test your design using the simulator before submitting it here.
  5. 100% What high-level languages call goto is usually called a jump instruction in assembly language. Given this processor hardware design, add control states to the following to implement an unconditional branch instruction, Br immed, such that the next instruction executed will be the one at PC+(immed<<2). The shift left by two is multiplying by 4, the size of an instruction word. Note that an immediate value of 0 will cause the instruction immediately after the Br to execute next, because the PC is incremented by 4 before the Br instruction is loaded into the IR. You should add initial values and test your design using the simulator before submitting it here. (Hint: although IRimmedout can be used, there is an IRoffsetout control signal that is useful for this.)
  6. 100%, A particular program expressed in a particular ISA executes 100 ALU instructions, 10 Loads, 8 Stores, and 2 Branches. A simple, non-pipelined, implementation of that ISA takes 7 CPI for each ALU instruction, 20 CPI for each load, 10 CPI for each Store, and 10 CPI for each Branch. The original clock frequency is 2GHz. How many clock cycles would the program take to execute? How many nanoseconds would the program take to execute?
  7. 100%, Given the circumstances described in question 1 above, which of the following three changes would yield at least 2X speedup?
    A new compiler reduces the number of ALU instructions from 100 to 20
    An improved design reduces the CPI for ALU instructions from 7 to 2
    New VLSI fabrication technology changes the clock period to 1ns
    Any of the above three would suffice to give at least 2X speedup
    None of the above three would suffice to give at least 2X speedup
  8. 100%, What is a synthetic benchmark and why might such a thing be useful?
  9. 100% Given this processor hardware design and the control sequence below, describe in words (or C-like pseudo code) the function of the instruction xyzzy immed(rt). 
    when op(0x3f) op(1) Xyzzy

Start:
 PCout, MARin, MEMread, Yin
 CONST(4), ALUadd, Zin, UNTILmfc
 MDRout, IRin
 Zout, PCin, JUMPonop
 HALT /* Should end here on undecoded op */

Xyzzy:
 SELrt, REGout, Yin
 IRimmedout, ALUadd, Zin
 Zout, MARin, MEMread
 CONST(-1), Yin, UNTILmfc
 MDRout, ALUxor, Zin
 Zout, MDRin, MEMwrite, JUMP(Start)

  10. 100% Given the xyzzy immed(rt) instruction as defined above, and assuming that a memory load request takes 4 clock cycles to complete (after MEMread has been issued), how many CPI would each xyzzy instruction require? You may use the simulator to get or check your answer. In any case, give and briefly explain your answer here:
  11. 100% Given this processor hardware design, suppose that the following control state is the limiting factor in determining the maximum clock speed. Given that the propagation delay associated with SELrs is 8ns, REGout is 4ns, MDRin is 2ns, ALUadd is 16ns, and Zin is 1ns, what is the period (in nanoseconds) of the fastest allowable clock? You may use the simulator to get or check your answer. In any case, give and briefly explain your answer here: 
    SELrs, REGout, MDRin, ALUadd, Zin

  12. 100%, A particular program consists of two functions, a() and b(). Initially, a() takes 750 clock cycles and b() takes 250 clock cycles. What is the maximum possible overall speedup that could be obtained by making changes that only affect the execution speed of a()?

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EE380 Computer Organization and Design.