EE380 Assignment 1 Solution

100% Here's something you know from EE280: Which of the following logic equations implements a multiplexor with two inputs, i0 and i1, and one select line, s?
((s OR (NOT i0)) AND (s OR i1))
((s AND (NOT i0)) OR (s AND i1))
((s AND (NOT i1)) OR (s AND i0))
((i0 AND (NOT s)) OR (i1 AND s))
((i1 AND (NOT s)) OR (i0 AND s))
100% Which of the following four statements is false?
Registers often are built using D flip-flops.
A one-bit SRAM cell is physically smaller than a one-bit DRAM cell.
A multiplexor can be implemented using a decoder and tri-state drivers.
Open-collector logic is the prefered method used to ensure that only one of multiple outputs connected to the same bus wire is active at any point in time.
None of the above is false.
100% Given this processor hardware design, add control states to the following to implement a bitwise AND instruction (as decoded by the when below), such that and rd,rs,rt yields rd=(rs AND rt). You should add initial values and test your design using the simulator before submitting it here.
when (op()+shamt()+funct()) funct(32) Add when (op()+shamt()+funct()) funct(36) And Start: PCout, MARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRout, IRin Zout, PCin, JUMPonop HALT /* Should end here on undecoded op */ Add: SELrs, REGout, Yin SELrt, REGout, ALUadd, Zin Zout, SELrd, REGin, JUMP(Start) And: /* YOUR CODE GOES HERE! */ SELrs, REGout, Yin SELrt, REGout, ALUand, Zin Zout, SELrd, REGin, JUMP(Start)
100% Given this processor hardware design, add control states to the following to implement a memory AND instruction (as decoded by the when below), such that Mand rs,immed(rt) yields memory[rt + immed] = (rs & memory[rt + immed]). Note that the code given below already implements MIPS "load word" and "store word" instructions... your control logic should work like load, AND the value from register rs, and store the result. You should add initial values and test your design using the simulator before submitting it here.
when (op()) {lw} Lw when (op()) {sw} Sw when (op()) op(1) Mand Start: PCout, MARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRout, IRin Zout, PCin, JUMPonop HALT /* Should end here on undecoded op */ Lw: SELrt, REGout, Yin IRimmedout, ALUadd, Zin Zout, MARin, MEMread /* MAR=rt+immed */ UNTILmfc MDRout, SELrs, REGin, JUMP(Start) Sw: SELrs, REGout, MDRin /* MDR=rs */ SELrt, REGout, Yin IRimmedout, ALUadd, Zin Zout, MARin, MEMwrite, JUMP(Start) /* MAR=rt+immed */ Mand: /* YOUR CODE GOES HERE! */ SELrt, REGout, Yin IRimmedout, ALUadd, Zin Zout, MARin, MEMread UNTILmfc, SELrs, REGout, Yin MDRout, ALUand, Zin Zout, MDRin, MEMwrite, JUMP(Start)
100% What high-level languages call goto is usually called a jump instruction in assembly language. Given this processor hardware design, add control states to the following to implement an unconditional branch instruction, Br immed, such that the next instruction executed will be the one at PC+(immed<<2). The shift left by two is multiplying by 4, the size of an instruction word. Note that an immediate value of 0 will cause the instruction immediately after the Br to execute next, because the PC is incremented by 4 before the Br instruction is loaded into the IR. You should add initial values and test your design using the simulator before submitting it here. (Hint: although IRimmedout can be used, there is an IRoffsetout control signal that is useful for this.)
when (op()+rs()+rt()) op(4) Br Start: PCout, MARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRout, IRin Zout, PCin, JUMPonop HALT /* Should end here on undecoded op */ Br: /* YOUR CODE GOES HERE! */ IRoffsetout, Yin /* many ways to do this! */ PCout, ALUadd, Zin Zout, PCin, JUMP(Start)

Computer Organization and Design.