EE380 Assignment 5 Solution

For this question, check all that apply. Consider the following two MIPS subset implementations:

Which of the following statements about how pipelining changes the architecture is true?
The Data Memory module could be the same circuit in both implementations
The Instruction Memory module could be the same circuit in both implementations
The ALU used to add 4 to the PC could be the same circuit in both implementations
The ALU used for operations like add and xor could be the same circuit in both implementations
Pipelined designs generally achieve higher performance than similar single-cycle designs by allowing a higher clock rate, but the clock rate with a 5-stage pipeline is generally somewhat less than 5X the speed of the single-stage design it was derived from (e.g., compare the two MIPs implementations given in question 1). Give one reason why the clock rate is less than 5X.
The primary issue is that the stages might not require the same delay; if the single-cycle design isn't broken into equal-delay parts, the clock is determined by the longest part. Another reason is that adding the buffers/registers between stages adds a little delay.
Consider executing each of the following code sequences on the pipelined MIPS implementation given below (which does not incorporate value forwarding):

Incidentally, both code sequences produce the same final results. Which of the following statements best describes the execution times you would expect to observe?
```
(A)  addi $t1,$t0,4
     lw   $t2,0($t0)
     xor  $t2,$t2,$t3

(B)  lw   $t2,0($t0)
     addi $t1,$t0,4
     xor  $t2,$t2,$t3
```
(A) would be faster than (B)
(B) would be faster than (A)
the addi is essentially free in the (B) because it happens in what would have been a nop for the dependence on $t2
(A) would take the same number of clock cycles as (B)
Consider executing each of the following code sequences on the pipelined MIPS implementation given below:

Also consider executing them on this design with value forwarding logic and datapaths added. Which of the following statements best describes how the forwarding logic would alter the execution times?
```
(A)  addi $t1,$t0,4
     lw   $t2,0($t0)
     xor  $t2,$t2,$t3

(B)  lw   $t2,0($t0)
     addi $t1,$t0,4
     xor  $t2,$t2,$t3
```
Neither (A) nor (B) is affected by forwarding
Both (A) and (B) would be faster using forwarding
(A) is helped by 2 clocks, (B) only by 1
(A) would be faster using forwarding, (B) is not affected
(A) is not affected, (B) would be faster using forwarding
The execution time improvements due to forwarding depend on the values in the registers, not on the instructions being executed; thus, it is impossible to say how execution times for (A) and (B) are affected
The first time a modern processor executes a particular branch instruction, it must compute the target address by adding the offset encoded within the branch instruction to the PC value. However, if the same instruction is executed again soon enough, the processor does not have to recompute the target address. Which hardware structure implements this feature?
BTB
BTB is Branch Target Buffer
TLB
TLC
Data Cache
Instruction Cache
You might think this would help, but it doesn't hold the target address -- just the offset
Here is a diagram showing the internals of Intel's Nehalem processor. From that, you can see all sorts of details about how the processor is implemented. Several similar diagrams are here for other processors. On the WWW, find a similar type of architectural implementation diagram for any processor in current production. The diagram does not need to include everything on chip, but must show some detail suggesting how out-of-order execution is implemented within that processor's pipeline structure (e.g., the diagram must show instruction buffers/queues or renaming logic). Paste the URL of the diagram below; also give the name of that processor and state how you know that processor is in current production.
Too many options to list here... for the Nehalem linked above, there are instruction queues and a reorder buffer.
Of course, here at the University of Kentucky, we See Blue. The above blue logos represent three professional organizations that you should be seeing throughout your professional career. All three offer educational/training materials. Give the full name of each of these organizations that also publishes ethics guidelines.
All three publish ethics guidelines. ACM: Association for Computing Machinery IEEE: Institute of Electrical and Electronics Engineers NSPE: National Society of Professional Engineers You probably should join at least ACM or IEEE as a student, and think about EIT (Engineer In Training) and the FE exam
You may have noticed that lately a lot of small, portable, computing devices (e.g., tablets) are now coming with batteries in the form of pouches permanently glued inside rather than individually-packaged user-interchangeable batteries. Technically, this has the primary advantage that it provides somewhat better battery life for the same size and weight device. Briefly describe one negative broader impact of permanently glued-in batteries and include a URL for an article supporting your claim:
Glued-in pouch batteries allow maximum power with minimum weight, but are a bit of an environmental nightmare. The chemicals used are very toxic, and it is fairly common that the pouches rupture in disposal if not during use. In use, the pouches will commonly expand as gasses build up, and can press against other components causing potential ruptures and even explosions. There are many references -- here's a fairly scary pair: http://www.atbatt.com/batterytimes/dangerous-battery http://batteryuniversity.com/learn/article/pouch_cell_small_but_not_trouble_free

Computer Organization and Design.