References: Verilog

You might remember some of this from CPE280 or CPE282, but we're not betting on that. Here are the basics for using Verilog.

It is worth noting that the particular Verilog we will use is Icarus Verilog, which is an open-source toolchain that is very faithful to the Verilog standard. Tools from Xilinx, for example, are not as full implementations of Verilog, so some things we discuss here may be unsupported in whatever toolchain you would use outside of this course. For example, the Xilinx tools are known to have problems with recursive modules.

Also note that the textbook does not discuss Verilog. The materials linked here are your primary reference.

• Slides overviewing Verilog for CPE380
• Icarus Verilog (iverilog and vvp) is the primary tool we'll be using for compiling and simulating Verilog code. It is actually part of gEDA. Note that you can install it on Ubuntu Linux systems by simply selecting it in the Software Center or Synaptic -- it's a standard part of the Ubuntu distribution, as well as having been ported to Windows, etc.
• Icarus Verilog Simulator CGI Interface created by Professor Dietz and used for Verilog code throughout this course
• EDA playground is an alternative WWW interface for running Icarus Verilog... and various other tools including some commercial simulators. Requires Log In for use, but registration is free.
• ASIC World has a multitude of really nicely prepared materials showing how to use Verilog
• If you have time, I strongly recommend watching Veritasium's hour-long video, The World's Most Important Machine, which gives the detailed history of development of ASML's EUV technology, which is used for creating the nanoscale structures of all of the lastest chips. Back when Prof. Dietz learned about VLSI, high-end chips generally followed a 5um design rule -- which was feasible with light. After all, visible light goes from about 780nm to 380nm. Now, design rules are much more complex than just specifying one key dimension, but feature sizes are more than three orders of magnitude smaller, often around 2nm (around ten atoms). In other words, chips can now hold millions of times more components in the same area, and this ASML technology is the main reason why.
• Is EUV lithography technology where Moore's Law will end? I wouldn't bet against Moore's Law continuing for a while yet, although nobody knows for sure. X-Ray lithography might be next. US company Substrate has some wild-sounding claims that could be either the future or a fraud. A more obvious way to keep things going involves various technologies making bigger chips by combining multiple dies, and various methods are quietly becoming commonplace...