References: EE380 Simple Memory Overview

Recall that the processor interfaces to memory as:

The read/~write line is a 1 for reading, 0 for writing. Strobe is pulsed when the memory address lines are valid. If the operation is a read, then MFC is set by the memory when it has completed fetching (reading) data for the processor, at which time data becomes valid for the processor to use.

Although memory can be constructed using decoders and multiplexors for access, it is common practice to use tri-state logic in place of a multiplexor. Tri-state logic also is used to build busses. Here's a little diagram reminding you how tri-state logic works:

Remember that the Z state is essentially "disconnect" -- it is NOT logic 1 nor logic 0, although a TTL input will read it as a 1 because an unconnected input is internally pulled high in the TTL input stage.

The resulting basic memory structure is something like:


EE380 Computer Organization and Design.