Testing Reference Material

Testing is a huge part of digital design -- and generally the most expensive part. Here are a few links to things about testing.

Covered

This is the primary tool we are reviewing for analysis of test coverage. The key is not really use of this tool, but creation of a test plan consistent with the concepts this tool helps process.

Slides on Design for Testability

Slides made by Prof. Dietz on the testing stuff you should know, but don't need to apply, in this course

Mark Horowitz slides on Design for Testability

I'm not an expert on digital circuit testing, but here are slides from someone who is. Similar to the slides above, but lower-level with scary analog details.

JTAG info site

A good source of details about JTAG, which is very widely used as a scan/edge interface, not just for programming FPGAs, etc.

On the loading of memories...

One of the uglier aspects of testing Verilog code is the initialization of memories. You'd like this to be done from a testbench, but it isn't really feasible because the testbench doesn't have access to memories instantiated in other modules. Consider:

module memory();
reg [15:0] mem[0:256];
integer a;
initial begin
 $readmemh("mem.vmem", mem);
 for (a=0; a<256; a=a+1) begin
  $display("%x:\t%x", a, mem[a]);
 end
end
endmodule

Where mem.vmem contains:

@0001
1234
5678
@0010
abcd