EE380 Practice Assignment 5

This is not a graded assignment, but should help you to study for the final exam. The solution for this is here.

For this question, check all that apply. Consider the following two MIPS subset implementations:

Which of the following statements about how pipelining changes the architecture is true?
The Data Memory module could be the same circuit in both implementations
The Instruction Memory module could be the same circuit in both implementations
The ALU used to add 4 to the PC could be the same circuit in both implementations
The ALU used for operations like add and xor could be the same circuit in both implementations
Pipelined designs generally achieve higher performance than similar single-cycle designs by allowing a higher clock rate, but the clock rate with a 5-stage pipeline is generally somewhat less than 5X the speed of the single-stage design it was derived from (e.g., compare the two MIPs implementations given in question 1). Give one reason why the clock rate is less than 5X.
Consider executing each of the following code sequences on the pipelined MIPS implementation given below (which does not incorporate value forwarding):

Incidentally, both code sequences produce the same final results. Which of the following statements best describes the execution times you would expect to observe?
```
(A)  addi $t1,$t0,4
     lw   $t2,0($t0)
     xor  $t2,$t2,$t3

(B)  lw   $t2,0($t0)
     addi $t1,$t0,4
     xor  $t2,$t2,$t3
```
(A) would be faster than (B)
(B) would be faster than (A)
(A) would take the same number of clock cycles as (B)
Consider executing each of the following code sequences on the pipelined MIPS implementation given below:

Also consider executing them on this design with value forwarding logic and datapaths added. Which of the following statements best describes how the forwarding logic would alter the execution times?
```
(A)  addi $t1,$t0,4
     lw   $t2,0($t0)
     xor  $t2,$t2,$t3

(B)  lw   $t2,0($t0)
     addi $t1,$t0,4
     xor  $t2,$t2,$t3
```
Neither (A) nor (B) is affected by forwarding
Both (A) and (B) would be faster using forwarding
(A) would be faster using forwarding, (B) is not affected
(A) is not affected, (B) would be faster using forwarding
The execution time improvements due to forwarding depend on the values in the registers, not on the instructions being executed; thus, it is impossible to say how execution times for (A) and (B) are affected
The first time a modern processor executes a particular branch instruction, it must compute the target address by adding the offset encoded within the branch instruction to the PC value. However, if the same instruction is executed again soon enough, the processor does not have to recompute the target address. Which hardware structure implements this feature?
BTB
TLB
TLC
Data Cache
Instruction Cache

Computer Organization and Design.