Before discussing the processor architecture, it is useful to note that there is a complete cycle-by-cycle simulator available via a WWW form interface at http://garage.ece.engr.uky.edu:10043/cgi-bin/simple.cgi. That simulator can be used to write and test your own control sequences.
Inside the processor, there are a variety of function units and registers connected to each other by one or more datapaths (e.g., busses). The control is responsible for sequencing the RTL (register transfer level) operations that implement each instruction in the ISA (instruction set architecture). Let's look inside this very simple implementation of the processor:
The red lines communicate between the processor and the memory. Blue lines are internal, dedicated, electrical connections; in contrast, green lines represent connections that can be made or broken as the control specifies. Let's look at each of the control signals and define what they mean:
| REGISTER control signal | Effect |
|---|---|
| ALUadd | Configures the ALU to add its inputs |
| ALUand | Configures the ALU to bitwise AND its inputs |
| ALUxor | Configures the ALU to bitwise eXclusive OR its inputs |
| ALUor | Configures the ALU to bitwise OR its inputs |
| ALUsll | Configures the ALU to shift left logical; the result is (bus << Y) |
| ALUslt | Configures the ALU to compare its inputs; the result is (Y < bus) |
| ALUsrl | Configures the ALU to shift right logical; the result is (bus >> Y) |
| ALUsub | Configures the ALU to subtract the bus input from Y |
| CONST(value) | Places the constant value onto the bus |
| HALT | Halt the machine (stop the simulator without error) at the end of the current state |
| IRaddrout | Tri-state enables the portion of the Instruction Register that contains the (26 bit, MIPS "J" format) address, along with the top 6 bits of the Program Counter, to be driven onto the bus |
| IRimmedout | Tri-state enables the portion of the Instruction Register that contains the (16 bit, MIPS "I" format) 2's complement immediate value to be sign-extended to 32 bits and driven onto the bus |
| IRin | Latches the bus data into the Instruction Register at the trailing edge of the clock cycle |
| IRoffsetout | Tri-state enables the Instruction Register's shifted and sign extended value from the offset field to be driven onto the bus (used for branches) |
| JUMP(label) | Microcode jump to label |
| JUMPonop | Microcode jump to label named like the opcode; e.g., if an "Addi" is in the IR, jumps to the microcode label Addi |
| MARin | Latches the bus data into the Memory Address Register at the trailing edge of the clock cycle |
| MARout | Tri-state enables the Memory Address Register's output to be driven onto the bus |
| MDRin | Latches the bus data into the Memory Data Register at the trailing edge of the clock cycle |
| MDRout | Tri-state enables the Memory Data Register's output to be driven onto the bus |
| MEMread | Initiate a memory read from the address in the MAR; here, you may assume that the memory will take 2 clock cycles to respond |
| MEMwrite | Initiate a memory write using the data in the MDR and the address in the MAR; in this simple design, you may assume that a memory write takes precisely 1 clock cycle |
| PCin | Latches the bus data into the Program Counter at the trailing edge of the clock cycle |
| PCinif0 | Only if the value in Z is zero, latch the bus data into the Program Counter at the trailing edge of the clock cycle |
| PCout | Tri-state enables the Program Counter's output to be driven onto the bus |
| REGin | Latches the bus data into whichever register is selected by SELrs, SELrt, or SELrd; the value is latched at the trailing edge of the clock cycle |
| REGout | Tri-state enables the output of whichever register is selected by SELrs, SELrt, or SELrd; the selected value is driven onto the bus |
| SELrs | Selects the rs field of the IR to be used to control the register file's decoder |
| SELrt | Selects the rt field of the IR to be used to control the register file's decoder |
| SELrd | Selects the rd field of the IR to be used to control the register file's decoder |
| UNTILmfc | Repeat this state until the memory has issued a memory fetch complete signal, indicating that the fetched value will be valid to read from the MDR in the next clock cycle |
| Yin | Latches the bus data into the Y register at the trailing edge of the clock cycle; this register is needed because, with only one bus, one of the two operands for a binary operation (e.g., Add) must come from somewhere other than the bus |
| Yout | Tri-state enables the Y register's output to be driven onto the bus |
| Zin | The ALU is always producing a result, but we only make note of that result if we latch the ALU's output into the Z register at the trailing edge of the clock cycle |
| Zout | Tri-state enables the Z Register's output to be driven onto the bus |
Computer Organization and Design.