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For this question, check all that apply.
Which of the following five statements about current computer
hardware is/are true?
A hard disk should outlast an SSD in an application that is continually rewriting data
A modern processor typically runs with a clock period under 1ns
Cost of a chip tends to dramatically increase with a larger die
An optical mouse actually contains a high-speed camera
Main memory in a PC is volatile
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For this question, check all that apply.
Which of the following five choices is/are
among the "eight great ideas" discussed in class and the text's first chapter?
Making families of compatible processors using the concept of an ISA
a good idea, but not one of the 8 listed...
Using guesses about program behavior to improve performance
Anticipating how computer technology will change over time
Programming in high-level languages
a good idea, but not one of the 8 listed...
Redundancy for reliability
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For this question, check all that apply.
Which of the following statements about how computer
technology has been changing over the last few decades is/are
true?
Supercomputers on the Top500 list nearly double performance every year
Compared to memory access speed, arithmetic is getting faster
Power consumption per transistor has been decreasing
unfortunately, not as fast as transistors/chip is increasing
The number of transistors/chip is increasing
Disk capacity has been getting larger
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For this question, check all that apply. Which of the
following things is/are associated with each
Instruction Set Architecture (ISA)?
Number of clock cycles/instruction
this is a free choice for implementors
Processor clock frequency
this is a free choice for implementors
Assembly language
Operating system
most OS can run on any of a variety of ISAs
Machine Code
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For this question, check all that apply.
Which of the following statements is/are true?
Zin only makes sense in a state where the ALU is doing something (e.g., ALUadd)
The MFC signal indicates that the most recent memory fetch request completed
A multiplexor can be built using a decoder and tri-state drivers
this is how we usually build them, and how me interface to a shared bus
DRAM usually takes less power per bit held than SRAM
DRAM holds charge on a capacitor, SRAM uses a digital feedback circuit (e.g., D flip-flop)
Allowing a few simultaneous readers from a bus is easy
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Given this processor
hardware design, add control states to the following to
implement an OR-with-immediate instruction (as decoded by the when
below), such that ori $rt,$rs,immed yields rt=(rs|immed).
This is actually a MIPS instruction, as we'll discuss later.
Hint: it's a lot like the addi given to you, isn't it?
You should add initial values and test your design using the
simulator before submitting it here.
You can test your code with:
MEM[0]={ori}+rs(9)+rt(10)+immed(3)
MEM[4]=0
$9=5
Register $10 should end-up holding the value
0x00000007 (7 decimal).
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Exchange instructions are commonly used for synchronizing
multiple processes sharing a processor. Given this processor
hardware design, add control states to the following to
implement an exchange-with-memory (as decoded by the when
below), such that xchg $rt,($rs) swaps the values in
mem[rs] and rt. Hint: you'll need to use a
temporary register... perhaps Y? You should add initial values
and test your design using the simulator before submitting it here.
You can test your code with:
MEM[0]=op(2)+rs(1)+rt(2)
MEM[4]=0
MEM[80]=42
$1=80
$2=601
Memory MEM[80] should end-up holding the value
0x00000259 (601 decimal) and register $2 should
end-up holding 0x0000002a (42 decimal).
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Given this processor
hardware design and the control sequence below, describe in
words (or C-like pseudo code) the function of the instruction
xyzzy $rt,$rs.
when op() op(1) Xyzzy
Start:
PCout, MARin, MEMread, Yin
CONST(4), ALUadd, Zin, UNTILmfc
MDRout, IRin
Zout, PCin, JUMPonop
HALT /* Should end here on undecoded op */
Xyzzy:
SELrs, REGout, Yin
CONST(-1), ALUadd, Zin
Zout, ALUand, Zin
Zout, ALUxor, Zin
Zout, SELrt, REGin, JUMP(Start)
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Given the xyzzy $rt,$rs instruction as defined above,
and assuming that a memory load request takes 2 clock
cycles to complete (after MEMread has been
issued), how many clock cycles would it take to execute each
xyzzy instruction? You may use the simulator to get or check your answer. In any case,
give and briefly explain your answer here:
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Given this processor hardware design, suppose that the following
control state is the limiting factor in determining the maximum
clock speed. Given that the propagation delay associated with
Zin is 1ns,
CONST(1) is 2ns,
REGin is 4ns,
SELrd is 8ns, and
ALUadd is 16ns,
what is the period (in nanoseconds) of the fastest allowable
clock? You may use the simulator to get or check your answer. In any case,
give and briefly explain your answer here:
ALUadd, CONST(1), Zin, SELrd, REGin
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Given this processor
hardware design, add control states to the following to
implement a multiply-by-4 instruction (as decoded by the when
below), such that mul4 rd makes rd=4*rd;.
Note that there is no multiplier per se in the ALU.
You should add initial values and test your design using the
simulator before submitting it here.
You can test your code with:
MEM[0]=op(1)+rd(5)
MEM[4]=0
$5=2
Register $5 should end-up holding the value
0x00000008 (8 decimal)
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What high-level languages call goto is usually called a
jump instruction in assembly language. The catch is that you
can't have a 6-bit opcode and a 32-bit (immediate) memory
address fit in one 32-bit instruction. MIPS handles this a
little strangely, so let's make a more normal jump instruction
called jump, which takes two words. The first
is the instruction with the opcode, the second is just the
32-bit jump target address. Thus, jump 0x12345678 would
be encoded as two words: 0x10000000 and
0x12345678. Executing that instruction would make the
next instruction be taken from memory address
0x12345678. Add states to the following to implement
the jump instruction.
You can test your code with:
MEM[0]=op(32) /* Jmp */
MEM[4]=800 /* to address 800 */
MEM[800]=0
The simulator should stop after failing to decode the instruction fetched from
MEM[800], at which time the PC should hold 804, which is 0x00000324.
