Preliminary Syllabus:
Fall 2017 EE480 (AKA CS480, CPE480)
Computer Architecture

Instructor: Professor Hank Dietz
Office: 203 Davis Marksbury Building
Home URL:
Course URL (watch errata for changes):
Course Meetings: MWF 3:00-3:50 in room 203 Ralph G Anderson.
Course Text: Computer Architecture, Fifth Edition: A Quantitative Approach, Hennessy & Patterson, Morgan Kaufmann publisher, 2012.
We will not be following this text very closely, nor assigning homework from it... but it is the standard reference for courses like this and can be of help: it is recommended, not required. Other texts/materials may be added to this syllabus during the semester.


This course focuses on general-purpose and advanced programmable computer processor architectures; their design, engineering development and validation; and low-level system software. Topics include general-purpose programmable stack, accumulator, memory-register, memory-memory, high performance RISC type architectures, multiprocessor and special-purpose computer architectures. Peripheral devices such as disk arrays, NICs, video/audio and other devices may be covered. Topics also include interrupt processing, assembly language programming techniques, assemblers, linkers, and loaders. Design, development, engineering, and Hardware Description Language (HDL) simulation validation/verification of general-purpose and special-purpose programmable architectures via use of HDLs is addressed. Prereq: EE 280 and EE/CS 380 or consent of instructor. EE 281 would be a helpful prerequisite.

In many ways, the content of EE480 is very similar to that of EE380, but with one huge difference: what EE380 overviews, you will work with in-depth here, even specifying hardware implementation details to the gate level. You've no doubt heard that EE480 requires you to complete a relatively large-scale processor design project using Verilog -- yes, you will. In Fall 2016, we made a variety of significant changes to this course. Many of the changes aimed to improve the success rate of students in the class, while other were steps toward adjusting EE480 to better fit with the new curriculum structure that will be starting with the common first year for engineering. Upcoming changes affecting Computer Engineering include significant restructuring of the Sophomore year courses and making both EE380 and EE480 be required only for Computer Engineering majors... so EE380 is changing too, allowing the EE380+EE480 pair to be rebalanced to be more effective. In sum, expect EE480 in this Fall 2017 semester to be a bit of a bumpy ride as we continue to evolve this course, but know that it's because we're trying to make it a better course, and your input on how the changes work isn't just welcome -- it's critically important to us.

Course Content

A very approximate overview of the lecture coverage is given in the following table. Reference materials will be noted via the course URL; you are expected to understand any material discussed in the lectures, cited from references, or presented via the course URL.

Topic Lectures (Minimum) Project Exam
Introduction 1
Using Verilog 3 Combinational Logic & Exhaustive Testing Midterm & Final
Simple Compiler 1 Midterm & Final
Assemblers 2 Assembler Midterm & Final
Instruction Set Design 3 Assembler, Simple Processor, & Testing Midterm & Final
Simple Processor Implementation 3 Midterm & Final
Testing Complex Designs 3 Midterm & Final
Verilog Compilation 2 Midterm & Final
Pipelining 6 Pipelined Simple Processor Final
Memory Hierarchy 5 Enhancement Of Pipelined Processor Final
Instruction-Level Parallelism 7 Final
Parallel Processing 3 Final

Note that the above table is a little short of the full number of class meetings. This is deliberate to allow some flexibility as there are many things new about the way this course is being taught this semester. The unlisted lectures will generally be spent on addition coverage of problem topics or review. For example, we expect to have at least one lecture period spent on review for each of the two exams.

Homework, Projects, Quizzes, & Exams

The current plan is to have a midterm (about 15% of your grade), a final (about 25%), and five or six homework assignments/projects (about 60%). However, I will apply the secondary rule that you cannot get more than one letter grade above the lower of your test and project averages.

The first two assignments are planned to be individual, but most of the assignments will be done in teams of approximately three students each. Teams will be pseudo-randomly assigned so that no two people will be on the same team for any two assignments. This mixing of teams was used in Spring 2017, and it worked well. Note that none of the projects will be the same as in Spring 2017 -- or any previous semester. In fact, we will use parts of the old sample solutions to help introduce the projects this semester. Aside from the processor design being different, the enhancement made in the last project also will be different; it was incorporation of a single-cycle 16-bit floating-point unit in Fall 2016.

Professor Dietz tries to minimize travel during the semester, but he probably will be presenting research at LCPC 2017 October 11-13, 2017 and at IEEE/ACM Supercomputing 2017, November 12-17, 2017. Arrangements are not yet final, so there may be some adjustment to the regular class meeting schedule. Any schedule changes, including changes made due to weather, are announced on the course website.

The course material is segmented into 2 exams, a midterm and a final, covering the material suggested in the table above. The final will be comprehensive, but with emphasis placed on the material that was not tested on the midterm. The midterm will be in class on a date to be announced in class and at the course URL; the final will be in the timeslot scheduled by the office of the registrar. The Fall 2017 EE380 final is listed as 1PM Monday, December 11, 2017.

The University of Kentucky gives very specific conditions that would justify taking an exam at other than the scheduled time and place, and we will honor all requests complying with university guidelines. Beyond that, we will try to accomodate any request to take an exam at other than the scheduled time provided that the request is made in writing or email before the scheduled exam time. In such cases, the course staff may elect to use a different format (e.g., an oral exam) for the specially-scheduled exam.


The grading in this course will generally follow the usual scale of "A" starting at 90%, "B" at 80%, "C" at 70%, and "D" at 65%; these grade thresholds will never be increased, but may be lowered slightly as the course staff find appropriate.

Mid-term grades are intended to help you know what grade your current trajectory is likely to result in for the complete course, and mid-term grades will be posted to myUK consistent with university guidelines. Mid-term grades will reflect performance on all work graded up to that point, which might or might not be directly predictive of final grades in that the relative weighting of exams and projects may be different (weighting the the first exam more heavily relative to the projects).

Homework/project solutions are posted to aid students in preparation for the upcoming assignments. You will generally have at least a week to do each homework. Two due dates will be stated for each assignment: a recommended due date (to keep you in-sync with the course lectures) and a date after which no submissions will be accepted (e.g., because the solution will be posted at that time). The first exam is generally graded and returned to the students, with answers reviewed either in class or in sessions scheduled specifically for that purpose. So that any possible grading errors can be consistently handled for all students, regrade requests (preferably in writing) must be made promptly and must be specific as to the reason a regrade is requested. At the option of the course staff, any work submitted for regrade may be re-evaluated in its entirety.


Students are expected to generally behave in an ethical manner, but violations will be treated as serious offenses. Altering graded exams and then submitting them for regrade is obviously unethical, but you do not need to be trying to enhance your grade in order for your behavior to be inappropriate. For example, attempts to break into computer accounts associated with this course or to falsely identify yourself are serious ethical violations even if there was no intent to "cheat" per se.

There are lots of study materials for this course, including old exams, widely available; using them as study aids is perfectly acceptable, but be warned that an apparent reuse of an old question usually has the question slightly reworded so that repeating the old answer will get no credit. Although students are encouraged to discuss course material with one another, everything you submit must be entirely your own original work. Similarly, for in-class exams that specify no textbooks, no calculators, etc., use of the banned resources is a serious offense.

University of Kentucky guidelines do not treat ethics violations as minor infractions. Violation of the policy can result in all involved students failing the course; more severe penalties also may be applied. Contact Professor Dietz beforehand if you have any doubts about how this policy might apply.

EE480 Advanced Computer Architecture.