Testing Reference Material
Testing is a huge part of digital design --
and generally the most expensive part.
Here are a few links to things about testing.
This is the primary tool we are reviewing for analysis
of test coverage. The key is not really use of this tool,
but creation of a test plan consistent
with the concepts this tool helps process.
Mark Horowitz slides on Design for Testability
I'm not an expert on digital circuit testing,
but here are slides from someone who is.
On the loading of memories...
One of the uglier aspects of testing Verilog code is the
initialization of memories. You'd like this to be done from
a testbench, but it isn't really feasible because the testbench
doesn't have access to memories instantiated in other modules.
reg [15:0] mem[0:256];
for (a=0; a<256; a=a+1) begin
$display("%x:\t%x", a, mem[a]);
Where mem.vmem contains:
Advanced Computer Architecture.