Verilog Reference Material
This course is primarily about the details of computer
architecture, and for that we need to get down to the level of
gates and signals. A heck of a lot of gates and signals. To
manage that complexity, we use a hardware description language
-- an HDL. In this course, the particular HDL we will use is
Verilog. Hardware design feels a lot like writing a program in
Verilog, but with basic constructs dealing with things like
wires and timing constraints, it's a very strange type of
An Introduction To Verilog (PDF)
These are the slides Prof. Dietz prepared and presented
in class as an introduction and overview of Verilog.
Icarus Verilog & Friends (PDF)
These are the slides Prof. Dietz prepared and presented in class
as an overview of some of the freely available tools
that are expected to be used for your Verilog projects in this
IEEE Standard for Verilog Hardware Description Language
Verilog began as a proprietary HDL around 1983.
Compared to most other hardware design tools at that time,
it is unusual in that it allows specifications to mix
a variety of different levels of hardware abstraction,
even including non-synthesizable programming constructs.
It is now one of the most commonly used HDLs.
This WWW site has a multitude of really nicely prepared
materials showing how to use Verilog. The only catch is that
it very freely mixes different levels all the way down to
transistors... be aware we don't want you doing that in EE480.
The gEDA project is developing a full GPL'd suite and toolkit of
Electronic Design Automation tools. There's a lot here, and it's
This is the primary tool we'll be using for compiling and
simulating Verilog code. It is actually part of gEDA.
Note that you can install it on Ubuntu Linux systems by
simply selecting it in the Software Center or Synaptic --
it's a standard part of the Ubuntu distribution, as well
as having been ported to Windows, etc.
Icarus Verilog Simulator CGI Interface
Don't want to deal with installing Icarus Verilog? Well, after
a little bit of C coding, Prof. Dietz has created a wrapper for
iverilog and vvp that allows you to use them
via a WWW browser form interface. There is even a scrolling
textual VCD trace browser; it might not be as pretty as
graphical waveform viewers, but it is fairly effective. As of
February 20, 2016, this interface now integrates coverage
anaylsis using covered, although to use that you
must create a VCD and include $dumpfile; precisely
once before specifying any other dump parameters. There
are a few restrictions, mostly involving file I/O, but it works
well enough to be usable for most things we will be doing in
Here's another WWW interface for running Icarus Verilog...
and various other tools including some commercial simulators.
Requires Log In for use, but registration is free.
Viewing Verilog Simulation Trace Waveforms
Well, comrades, here we have a choice of one graphical tool.
Fortunately, it's a pretty good one. Of course, the CGI
interface that Prof. Dietz made (see above) also includes a VCD
parser and can render traces textually for browsing.
This is a simple tool for viewing trace waveforms,
especially value change dump (VCD) files.
Schematics For Verilog Designs
There are a variety of ways to make schematics for a Verilog
design, but most involve manually creating the schematic. In
comparison, the Xilinx Verilog toolchain handles this task
fairly well... but Yosys is pretty useful as a fully automatic
tool and some of the manual drawing tools really can be quite
effective in drawing schematics. Why? It is quite easy for a
diagram automatically produced from Verilog to be so full of
details as to be unreadable. For documentation purposes, a good
schematic should abstract the design enough to make the overall
approach clear at a glance.
The Yosys Open SYnthesis Suite (what does the Y stand for?)
is an attempt to render Verilog to FPGAs, etc. In EE480, we
don't need to do that. However, it also can create schematics
from Verilog designs, and that's cool. This is also very
portable, free, code, but it's not in the usual Ubuntu
repositories (there's a special one for it).
This is another one of those very useful software tools out of
Bell Labs. It is a language and tools to generate graphs using
automatic layouts. Yosys uses it, and you might too:
the schematics Yosys generates from Verilog are editable graph
specifications for GraphViz.
This is a schematic capture program within gEDA (and generally
installed as part of gEDA). It has libraries of parts (e.g.,
7400-series TTL) that can easily be used to draw circuit
diagrams at the gate level and can maintain connections between
components as the components are moved doing manual layout.
KiCad is not just a schematic capture system, but integrates
electrical rule checks, netlist export, etc. In general, it is
more oriented toward board-level design. The tool within KiCad
that makes schematics is eeschema; it seems a tad less clever
than gschem, but is generally similar. Like Yosys, KiCad runs
on many systems, but it is not in the usual Ubuntu repositories
(it has its own to install from). It doesn't know about Verilog.
XCircuit is a drawing program written for unix/X11 (also running
on Windows under Cygwin X-Server). It is claimed to produce
"publishable-quality electrical circuit schematic diagrams and
related figures." This is not tied to Verilog in any way, but
is one of several viable method by which schematics to accompany
a Verilog design can be manually crafted.
If you've used a unix system to draw a simple diagram any time
in the last 30 years, there's a good chance you tried using xfig.
It is a very simple, dumb, graphical editor that is well known
for simply letting you do what you need to quickly and precisely.
There are parts libraries, but people usually just use the macro
facility in the tool. I've not recommended using xfig for decades,
but I have to admit that I often find myself using it because it
is the fastest way to get an accurately-dimensioned drawing made.
Of course, it doesn't know about Verilog.
Advanced Computer Architecture.