EE380 Assignment 4 Solution

100% For this question, check all that apply. In the single-cycle design shown in the above (rather large and very familiar) figure, which of the following signals are "don't cares" when executing a MIPS sw instruction?
Branch
No, needs to be 0
RegDst
ALUSrc
No, must be 1
MemRead
No, needs to be 0
MemtoReg
100% For this question, check all that apply. In the single-cycle design shown in the above (rather large and very familiar) figure, suppose that ALUSrc=1 and MemRead=0. Which of the following MIPS instructions might be executing?
sw $t0,4($t1)
lw $t0,4($t1)
Would need MemRead=1
ori $t0,$t1,2
beq $t0,$t1,l
Would need ALUSrc=0
add $t0,$t1,$t2
Would need ALUSrc=0
100% What is the logic formula for Z?

Z=(NOT(C) AND NOT(D)) OR (NOT(A) AND NOT(B) AND NOT(C))
100% What goal do VLIW, SuperScalar processing, and EPIC have in common?
Controlling multiple function units within a single instruction; instruction-level parallelism: multiple instructions executing simultaneously.

Computer Organization and Design.