Spring 2021 EE380 Assignment 4

Use this WWW form to submit your assignment. You may submit your assignment as many times as you wish; when the submission deadline is reached, your last recorded submission will be the one counted by the TA for grading.

Your account is
Your password is

1. For this question, check all that apply. We discussed a variety of methods for performing binary addition. Which of the following statements are true?
   Ripple Carry uses less circuitry than other methods
   Speculative carry tends to use less power than other comparably-fast methods
   Carry Select implements K-bit addition using three simultaneous (K/2)-bit additions
   Fast 31-input AND and OR gates would be useful in implementing 32-bit carry select
   It is possible to mix techniques, e.g., using ripple carry for 8-bit chunks within a 16-bit carry select
2. The following Verilog code implements and tests a module mulby7 that multiplies a 16-bit number by 7. However, it uses two additions in computing that result, which would imply two 16-bit adders must be built. Using Booth's algorithm, rewrite the assign r line to use a single subtract instead of two adds. You must only change that single line of Verilog code. You can test your Verilog design by copying the code into the Icarus Verilog Simulator CGI Interface.
   module mulby7(r, a); input [15:0] a; output [15:0] r; assign r = a + (a << 1) + (a << 2); endmodule module testit; reg [15:0] a, refr; wire [15:0] r; mulby7 mul(r, a); initial begin a = 0; repeat (65536) begin #1 refr = a * 7; if (r != refr) $display(a, " * 7 = ", refr, ", but got ", r); a = a + 1; end end endmodule
3. For this question, check all that apply. Which of the following statements about the Verilog implementations of ALU operations (as discussed in the lecture slides) are true?
   Given reg [2:0] a=1;, the value of {1'b1,a} is 4'b1001
   An N-bit barrel shifter can shift by any number of bit positions in O(log₂N) time
   The Verilog code assign a=(|b); is logically equivalent to assign a=(b!=0);
   Use of recursion in Verilog is only allowed for simulation; recursive designs are never synthesizable
   A parametric design, such as the the parametric ripple carry adder, will generate much more complex hardware in implementing an 8-bit ripple carry adder than the 8-bit non-parametric version.
4. For this question, check all that apply. In mathematics, both addition and multiplication are associative; for example, a+(b+c) gives the same value as (a+b)+c. Assuming no values go out of range, is addition and multiplication are associative for 2's complement binary integers and for IEEE-format floating-point values? Mark all the operations that are associative.
   32-bit integer addition
   32-bit (single) floating-point addition
   64-bit (double) floating-point addition
   32-bit (single) floating-point multiplication
   64-bit (double) floating-point multiplication
5. For this question, check all that apply. Which of the following statements about computer arithmetic are true?
   A single-precision float is just the top 32 bits of a 64-bit double
   Multiply of 8-bit integers is sometimes done using a ROM lookup table
   Catastrophic cancellation happens when adding two numbers with very different exponents
   All 32-bit 2's complement integer values can be precisely represented as normal-form float values
   If MIPS register $t0 holds a normal floating-point value, it can be negated by

   lui $t1,0x8000
   xor $t0,$t0,$t1
   

6. 
   
   For this question, check all that apply. In the single-cycle design shown in the above (rather large and very familiar) figure, which of the following signals could be 1 (could does not mean must!) when executing a MIPS beq instruction?
   Branch
   RegDst
   ALUSrc
   RegWrite
   MemtoReg
7. 
   
   For this question, check all that apply. In the single-cycle design shown in the above (rather large and very familiar) figure, suppose that RegDst=1 and RegWrite=1. Which of the following MIPS instructions might be executing?
   sw $t0,4($t1)
   lw $t0,4($t1)
   beq $t0,$t1,l
   andi $t0,$t1,2
   add $t0,$t1,$t2
8. 
   
   For this question, check all that apply. We implemented the single-cycle design shown in the above (rather large and very familiar) figure as this Verilog code. Suppose that I wanted to implement a new "load indexed" instruction, ldx $rd,$rt($rs), that implements $rd=memory[$rt+$rs]. Which of the following changes to our single-cycle MIPS implementation would be appropriate? You should assume an appropriate `define LDX was used to define the opcode, and that the instruction is of type RTYPE.
   The assign ALUSrc must be changed
   The assign MemtoReg should be changed
   The opcode for ldx can use the FUNCT field
   In module alu, ldx should use res = (top + bot)
   It will be necessary to change things inside always @(posedge clk) in module processor
9. 
   
   We implemented the single-cycle design shown in the above (rather large and very familiar) figure as this Verilog code. In order to test the system, various instructions were placed into memory locations starting at m[0]. Instead of `RPACK(m[0], 2, 3, 1, 0, `ADDU), what Verilog code would you write to make the instruction in m[0] encode a test case for the ldx $rd,$rt($rs) instruction (opcode `LDX) as described in the previous question: ldx $3,$2($1)? Your answer can use one of the macros defined for initializing instructions, or you can write Verilog code that directly fills the fields of m[0].

10. What is the logic formula for X?
    
    

Although this is not a secure server, users are bound by the UK code of conduct not to abuse the system. Any abuses will be dealt with as serious offenses.