Icarus Verilog Simulator CGI Interface

This is the parametric BITS-bit shift-and-subtract divider (divide with remainder) example from these slides.

module div(ready, q, r, n, d, reset, clk);
parameter BITS=8;
input [BITS-1:0] n, d;
input reset, clk;
output wire [BITS-1:0] q, r;
output reg ready;
reg [2*BITS-1:0] rq;
reg [BITS-1:0] state, s;
reg lsb;

assign q = rq[BITS-1:0];
assign r = rq[2*BITS-1:BITS];

always @(posedge clk or posedge reset) begin
  if (reset) begin
    ready <= 0;
    state <= 1;
    rq <= { {BITS{1'b0}}, n };
  end else begin
    if (state) begin
      if (d == 0) begin
	rq <= 0; // really divide by 0 error
	ready <= 1;
      end else begin
	if (rq[2*BITS-2:BITS-1] >= d) begin
	  s = rq[2*BITS-2:BITS-1] - d;
	  lsb = 1;
	end else begin
	  s = rq[2*BITS-2:BITS-1];
	  lsb = 0;
	end
	rq <= { s, rq[BITS-2:0], lsb };
        state <= {state[BITS-2:0], 1'b0};
      end
    end else begin
      ready <= 1;
    end
  end
end
endmodule

module testbench;
parameter BITS=8;
reg [BITS-1:0] a, b;
reg [BITS-1:0] refq, refr;
wire [BITS-1:0] q, r;
wire rdy;
reg reset = 0, clk = 0;
integer tested=0, wrong=0;

div #(BITS) mydiv(rdy, q, r, a, b, reset, clk);

initial begin
  a=0;
  repeat (1<<BITS) begin
    b=0;
    repeat (1<<BITS) begin
      #1 reset = 1;
      #1 reset = 0;
      while (!rdy) begin
        #1 clk = ~clk;
        #1 clk = ~clk;
      end
      refq = a / b;
      refr = a % b;
      tested=tested+1;
      if ((refq != q) || (refr != r)) begin
	$display("Wrong: %d/%d is %d,%d, but got %d,%d", a, b, refq, refr, q, r);
	wrong=wrong+1;
      end
      b = b + 1;
    end
    a = a + 1;
  end
  $display("%d cases tested, %d wrong", tested, wrong);
end
endmodule

The C program that generated this page was written by Hank Dietz using the CGIC library to implement the CGI interface.

Advanced Computer Architecture.