Icarus Verilog Simulator CGI Interface

This is the 8-bit ripple carry adder example from these slides.

// Full Adder
module fa(sum, cout, a, b, cin);
output sum, cout;
input a, b, cin;
wire aorb, gen, prop;
xor(sum, a, b, cin); // sum
and(gen, a, b);	     // generate
or(aorb, a, b);	     // propogate
and(prop, aorb, cin);
or(cout, gen, prop); // cout
endmodule

// Ripple carry addition, 8-bit
module add8(sum, cout, a, b, cin);
output [7:0] sum;
output cout;
input [7:0] a, b;
input cin;
wire [6:0] lcout;
fa fa0(sum[0], lcout[0], a[0], b[0], cin),
   fa1(sum[1], lcout[1], a[1], b[1], lcout[0]),
   fa2(sum[2], lcout[2], a[2], b[2], lcout[1]),
   fa3(sum[3], lcout[3], a[3], b[3], lcout[2]),
   fa4(sum[4], lcout[4], a[4], b[4], lcout[3]),
   fa5(sum[5], lcout[5], a[5], b[5], lcout[4]),
   fa6(sum[6], lcout[6], a[6], b[6], lcout[5]),
   fa7(sum[7], cout, a[7], b[7], lcout[6]);
endmodule

module testbench;
reg [7:0] a, b, refsum;
wire [7:0] sum;
reg cin, refcout;
wire cout;
integer tested=0, wrong=0;

add8 uut(sum, cout, a, b, cin);

initial begin
  a=0;
  repeat (256) begin
    b=0;
    repeat (256) begin
      cin=0;
      repeat (2) #1 begin
        {refcout, refsum} = a + b + cin;
        tested=tested+1;
        if ((refcout != cout) || (refsum != sum)) begin
	  $display("Wrong: %d+%d+%d is {%d,%d}, but got {%d,%d}", a, b, cin, refcout, refsum, cout, sum);
          wrong=wrong+1;
        end
        cin=1;
      end
      b = b + 1;
    end
    a = a + 1;
  end
  $display("%d cases tested, %d wrong", tested, wrong);
end
endmodule

The C program that generated this page was written by Hank Dietz using the CGIC library to implement the CGI interface.

Advanced Computer Architecture.