Binary Coded Decimal Adder

// 1-bit Full Adder module fa(co, s, a, b, ci); output co, s; input a, b, ci; assign s = (a ^ b ^ ci); assign co = ((a & b) | ((a | b) & ci)); endmodule // 4-bit BCD digit add module da(co, s, a, b, ci); output co; output [3:0] s; input [3:0] a, b; input ci; wire [4:0] c, t, w; // t = a + b + t fa g0(c[0], t[0], a[0], b[0], ci); fa g1(c[1], t[1], a[1], b[1], c[0]); fa g2(c[2], t[2], a[2], b[2], c[1]); fa g3(t[4], t[3], a[3], b[3], c[2]); // w = t + 6 assign w[0] = t[0]; fa g4(c[3], w[1], t[1], 1'b1, 1'b0); fa g5(c[4], w[2], t[2], 1'b1, c[3]); fa g6(w[4], w[3], t[3], 1'b0, c[4]); // over = (t >= 10) assign co = (t[4] | (t[3] & (t[2] | t[1]))); assign s = (co ? w : t); endmodule // 8-bit BCD add module bcdadd(s, a, b); output [7:0] s; input [7:0] a, b; wire [1:0] c; da d0(c[0], s[3:0], a[3:0], b[3:0], 1'b0); da d1(c[1], s[7:4], a[7:4], b[7:4], c[0]); endmodule // REFerence 8-bit BCD add module refbcdadd(s, a, b); output [7:0] s; input [7:0] a, b; wire [7:0] t; assign t = ((a[7:4] + b[7:4]) * 10) + a[3:0] + b[3:0]; assign s[7:4] = ((t / 10) % 10); assign s[3:0] = (t % 10); endmodule // TEST BENCH module testbench; reg [7:0] i, j, a, b; integer correct = 0; integer failed = 0; wire [7:0] v, vref; bcdadd uut(v, a, b); refbcdadd oracle(vref, a, b); initial begin i=0; repeat (100) begin a[7:4] = ((i / 10) % 10); a[3:0] = (i % 10); j=0; repeat (100) #1 begin b[7:4] = ((j / 10) % 10); b[3:0] = (j % 10); #1 begin if (v != vref) begin $display("Wrong: refbcdadd(%x,%x)=%x, but bcdadd was %x", a, b, vref, v); failed = failed + 1; end else begin correct = correct + 1; end j = j + 1; end end i = i + 1; end $display("All cases tested; %d correct, %d failed", correct, failed); $finish; end endmodule