16-Bit Floating Point Modules

The following is a set of 16-bit floating-point modules suitable for use in implementing this TACKY processor. They are NOT an implementation of the standard 16-bit half-precision floating-point, but rather implement just the bare minimum functionality for a format which is the top 16 bits of the standard 32-bit single-precision IEEE 754 format. Each basic operation appears to be a combinatorial module, although it's highly debatable if it would make sense to build hardware that way; after all, it assumes an 8x8 multiply is a combinatorial circuit, which it can be, but it isn't small if implemented that way.

This code was created February 19, 2019 by Henry Dietz, http://aggregate.org/hankd, and is distributed under CC BY 4.0, https://creativecommons.org/licenses/by/4.0/

This code has not yet been well-tested and may be corrected or enhanced, so watch the following revision history:

20190219: Created
20190222: Initial posting at this page
20190227: Fixed minor bugs in fadd, fmul; added testbench & VMEM1 ref data

Verilog source code:

// Floating point Verilog modules for CPE480 // Created February 19, 2019 by Henry Dietz, http://aggregate.org/hankd // Distributed under CC BY 4.0, https://creativecommons.org/licenses/by/4.0/ // Field definitions `define WORD [15:0] // generic machine word size `define INT signed [15:0] // integer size `define FLOAT [15:0] // half-precision float size `define FSIGN [15] // sign bit `define FEXP [14:7] // exponent `define FFRAC [6:0] // fractional part (leading 1 implied) // Constants `define FZERO 16'b0 // float 0 `define F32767 16'h46ff // closest approx to 32767, actually 32640 `define F32768 16'hc700 // -32768 // Count leading zeros, 16-bit (5-bit result) d=lead0s(s) module lead0s(d, s); output wire [4:0] d; input wire `WORD s; wire [4:0] t; wire [7:0] s8; wire [3:0] s4; wire [1:0] s2; assign t[4] = 0; assign {t[3],s8} = ((|s[15:8]) ? {1'b0,s[15:8]} : {1'b1,s[7:0]}); assign {t[2],s4} = ((|s8[7:4]) ? {1'b0,s8[7:4]} : {1'b1,s8[3:0]}); assign {t[1],s2} = ((|s4[3:2]) ? {1'b0,s4[3:2]} : {1'b1,s4[1:0]}); assign t[0] = !s2[1]; assign d = (s ? t : 16); endmodule // Float set-less-than, 16-bit (1-bit result) torf=a<b module fslt(torf, a, b); output wire torf; input wire `FLOAT a, b; assign torf = (a `FSIGN && !(b `FSIGN)) || (a `FSIGN && b `FSIGN && (a[14:0] > b[14:0])) || (!(a `FSIGN) && !(b `FSIGN) && (a[14:0] < b[14:0])); endmodule // Floating-point addition, 16-bit r=a+b module fadd(r, a, b); output wire `FLOAT r; input wire `FLOAT a, b; wire `FLOAT s; wire [8:0] sexp, sman, sfrac; wire [7:0] texp, taman, tbman; wire [4:0] slead; wire ssign, aegt, amgt, eqsgn; assign r = ((a == 0) ? b : ((b == 0) ? a : s)); assign aegt = (a `FEXP > b `FEXP); assign texp = (aegt ? (a `FEXP) : (b `FEXP)); assign taman = (aegt ? {1'b1, (a `FFRAC)} : ({1'b1, (a `FFRAC)} >> (texp - a `FEXP))); assign tbman = (aegt ? ({1'b1, (b `FFRAC)} >> (texp - b `FEXP)) : {1'b1, (b `FFRAC)}); assign eqsgn = (a `FSIGN == b `FSIGN); assign amgt = (taman > tbman); assign sman = (eqsgn ? (taman + tbman) : (amgt ? (taman - tbman) : (tbman - taman))); lead0s m0(slead, {sman, 7'b0}); assign ssign = (amgt ? (a `FSIGN) : (b `FSIGN)); assign sfrac = sman << slead; assign sexp = (texp + 1) - slead; assign s = (sman ? (sexp ? {ssign, sexp[7:0], sfrac[7:1]} : 0) : 0); endmodule // Floating-point multiply, 16-bit r=a*b module fmul(r, a, b); output wire `FLOAT r; input wire `FLOAT a, b; wire [15:0] m; // double the bits in a fraction, we need high bits wire [7:0] e; wire s; assign s = (a `FSIGN ^ b `FSIGN); assign m = ({1'b1, (a `FFRAC)} * {1'b1, (b `FFRAC)}); assign e = (((a `FEXP) + (b `FEXP)) -127 + m[15]); assign r = (((a == 0) || (b == 0)) ? 0 : (m[15] ? {s, e, m[14:8]} : {s, e, m[13:7]})); endmodule // Floating-point reciprocal, 16-bit r=1.0/a // Note: requires initialized inverse fraction lookup table module frecip(r, a); output wire `FLOAT r; input wire `FLOAT a; reg [6:0] look[127:0]; initial $readmemh0(look); assign r `FSIGN = a `FSIGN; assign r `FEXP = 253 + (!(a `FFRAC)) - a `FEXP; assign r `FFRAC = look[a `FFRAC]; endmodule // Floating-point shift, 16 bit // Shift +left,-right by integer module fshift(r, f, i); output wire `FLOAT r; input wire `FLOAT f; input wire `INT i; assign r `FFRAC = f `FFRAC; assign r `FSIGN = f `FSIGN; assign r `FEXP = (f ? (f `FEXP + i) : 0); endmodule // Integer to float conversion, 16 bit module i2f(f, i); output wire `FLOAT f; input wire `INT i; wire [4:0] lead; wire `WORD pos; assign pos = (i[15] ? (-i) : i); lead0s m0(lead, pos); assign f `FFRAC = (i ? ({pos, 8'b0} >> (16 - lead)) : 0); assign f `FSIGN = i[15]; assign f `FEXP = (i ? (128 + (14 - lead)) : 0); endmodule // Float to integer conversion, 16 bit // Note: out-of-range values go to -32768 or 32767 module f2i(i, f); output wire `INT i; input wire `FLOAT f; wire `FLOAT ui; wire tiny, big; fslt m0(tiny, f, `F32768); fslt m1(big, `F32767, f); assign ui = {1'b1, f `FFRAC, 16'b0} >> ((128+22) - f `FEXP); assign i = (tiny ? 0 : (big ? 32767 : (f `FSIGN ? (-ui) : ui))); endmodule // Testing module testbench; reg `FLOAT a, b; reg `WORD r; wire `FLOAT addr,mulr, recr, shir, i2fr; wire `INT f2ir, i, j, ia, ib, addri; reg `WORD ref[1024:0]; f2i myfa(ia, a); f2i myfb(ib, b); fadd myadd(addr, a, b); f2i myaddf(addri, addr); fmul mymul(mulr, a, b); frecip myrecip(recr, a); fshift myshift(shir, a, f2ir); f2i myf2i(f2ir, a); f2i myib(i, b); f2i myiadd(j, addr); i2f myi2f(i2fr, f2ir); initial begin $readmemh1(ref); r = 0; while (ref[r] != 0) begin a = ref[r]; b = ref[r+1]; #1 $display("Testing (int)%x = %d, (int)%x = %d", a, ia, b, ib); if (addr != ref[r+2]) $display("%x + %x = %x # %x", a, b, addr, ref[r+2]); if (mulr != ref[r+3]) $display("%x * %x = %x # %x", a, b, mulr, ref[r+3]); if (recr != ref[r+4]) $display("1 / %x = %x # %x", a, recr, ref[r+4]); r = r + 5; end end endmodule

VMEM file contents:

VMEM 0:
// Reciprocal fraction // lookup table, as VMEM @0000 00 7e 7c 7a 78 76 74 72 70 6f 6d 6b 6a 68 66 65 63 61 60 5e 5d 5b 5a 59 57 56 54 53 52 50 4f 4e 4c 4b 4a 49 47 46 45 44 43 41 40 3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30 2f 2e 2d 2c 2b 2a 29 28 28 27 26 25 24 23 23 22 21 20 1f 1f 1e 1d 1c 1c 1b 1a 19 19 18 17 17 16 15 14 14 13 12 12 11 10 10 0f 0f 0e 0d 0d 0c 0c 0b 0a 0a 09 09 08 07 07 06 06 05 05 04 04 03 03 02 02 01 01 00

VMEM 1:
@0000 3f80 3f80 4000 3f80 3f80 4000 3f80 4040 4000 3f00 4120 4120 41a0 42c8 3dcc 447a 447a 44fa 4974 3a83 c47a c47a c4fa 4974 ba83 447a c47a 0000 c974 3a83 c47a 447a 0000 c974 ba83 3dcc 4120 4121 3f7f 4120 4120 3dca 4121 3f7c 3dcc 4049 449a 449a 4571 3ea3 0000

The C program that generated this page was written by Hank Dietz using the CGIC library to implement the CGI interface.

Advanced Computer Architecture.