This is the multiplier example from these slides.
module mulBiQi(S,Clk,Clr,Bi,Qi,C,A,Q,P); input S,Clk,Clr; input[4:0]Bi,Qi; output C; output[4:0]A,Q; output[2:0]P; reg C; reg[4:0]A,Q,B; reg[2:0]P; reg[1:0]ps,ns; parameter T0=2'b00,T1=2'b01,T2=2'b10,T3=2'b11; wire Z; // lousy name, not same as z assign Z= ~|P; // nor reduction of P always @(negedge Clk or negedge Clr) if (~Clr) ps=T0; else ps<=ns; always @(S or Z or ps) case (ps) // next state logic T0: if (S) ns=T1; else ns=T0; T1: ns=T2; T2: ns=T3; T3: if (Z) ns=T0; else ns=T2; endcase always @(negedge Clk) case (ps) // next state logic T0: B<=Bi; // get multiplicand T1: begin // get multiplier, counter to 5 (bits) A <= 5'b00000; C <= 1'b0; P<=3'd5; Q<=Qi; end T2: begin // do add (verilog builds the adder!) P<=P-3'b001; if (Q[0]) {C,A}<=A+B; end T3: begin // shifts C<=1'b0; A<={C,A[4:1]}; A<={A[0],Q[4:1]}; end endcase endmodule module test_mulBiQi; reg S,Clk,Clr; reg[4:0]Bi,Qi; wire C; wire[4:0]A,Q; wire[2:0]P; mulBiQi mp(S,Clk,Clr,Bi,Qi,C,A,Q,P); initial begin S=0; Clk=0; Clr=0; #5 S=1; Clr=1; Bi=5'b10111; Qi=5'b10011; #15 S=0; end initial begin repeat (26) #5 Clk = ~Clk; end always @(negedge Clk) $strobe("C=%b A=%b Q=%b P=%b time=%0d",C,A,Q,P,$time); endmodule
The C program that generated this page was written by Hank Dietz using the CGIC library to implement the CGI interface.
Advanced Computer Architecture.