16-bit Absolute Value

// 1-bit Half Adder module ha(s, co, a, b); output s, co; input a, b; xor summer(s, a, b); and (co, a, b); endmodule // 16-bit Negate module neg(b, a); parameter BITS = 16; output [BITS-1:0] b; input [BITS-1:0] a; wire [BITS-1:0] c; ha g(b[0], c[0], 1, ~a[0]); genvar i; for (i=1; i<BITS; i=i+1) begin:bitpos ha g(b[i], c[i], c[i-1], ~a[i]); end endmodule // 16-bit Absolute Value module abs(b, a); parameter BITS = 16; output [BITS-1:0] b; input [BITS-1:0] a; wire [BITS-1:0] n; neg #(.BITS(BITS)) neg(n, a); assign b = (a[BITS-1] ? n : a); endmodule // REFerence 16-bit Absolute Value module refabs(b, a); parameter BITS = 16; output signed [BITS-1:0] b; input signed [BITS-1:0] a; assign b = ((a < 0) ? -a : a); endmodule // TEST BENCH module testbench; reg signed [15:0] a; wire signed [15:0] b, refb; integer correct = 0; integer failed = 0; abs #(.BITS(16)) uut(b, a); refabs #(.BITS(16)) oracle(refb, a); initial begin a = -32768; repeat (65536) begin #1 if (b != refb) begin $display("Wrong: refabs of %d was %d, but abs was %d", a, refb, b); failed = failed + 1; end else begin correct = correct + 1; end a = a + 1; end $display("All cases tested; %d correct, %d failed", correct, failed); $finish; end endmodule