Multi-Cycle TACKY

The following is a barely-tested sample solution that Prof. Dietz created for the multi-cycle implementation of this TACKY processor. It uses the slightly-mutant 16-bit top-half-of-32-bit-single floating-point implementation given here.

To begin, notice that the instruction encoding is slightly tricky. Basically, the idea was to separate-out the instructions into three easily recognized groups: ALU register operations, register operations not using the ALU, register with 8-bit immediate, and 8-bit immediate. The first two groups allow packing two instructions into one instruction word, the last two don't. The encoding was arranged so that the top 2 bits of the 5-bit first opcode field must be 2'b11 if the instruction stands alone. Those instructions are handled by their own unique states. The packed instructions are handled by the sequence of two states, Pack0 and Pack1, which is slower than it needs to be, but works with just one instance of the ALU -- and the ALU is pretty large, so that's not unreasonable. Note that the ALU also determines if the ALU operation was legal, and treats other packed operations as NOPs. Thus, every instruction word is processed fairly straightforwardly in either 3 or 4 cycles with Start and Decode common to all.

The following is the AIK assembler specification for how the opcodes are mapped in the Verilog code of the sample solution.

AIK source code:

; Packable register operations .rop $.r0, .rop $.r1 := .this:5 .r0:3 .rop:5 .r1:3 .alias .rop { 0x00 a2r r2a add and cvt div mul not or sh slt sub xor 0x10 jr lf li st } ; Register and 8-bit immediate .ri8op $.r,.i8 := .this:5 .r:3 .i8:8 .alias .ri8op 0x18 cf8 ci8 jnz8 jz8 ; 8-bit immediate .i8op .i8 := .this:5 0:3 .i8:8 .alias .i8op 0x1c jp8 pre sys ; Macros cf $.r,.i16 := pre:5 0:3 (.i16>>8):8 cf8:5 .r:3 .i16:8 ci $.r,.i16 := pre:5 0:3 (.i16>>8):8 ci8:5 .r:3 .i16:8 jnz $.r,.i16 := pre:5 0:3 (.i16>>8):8 jnz8:5 .r:3 .i16:8 jp .i16 := pre:5 0:3 (.i16>>8):8 jp8:5 0:3 .i16:8 jz $.r,.i16 := pre:5 0:3 (.i16>>8):8 jz8:5 .r:3 .i16:8 ; Pre-defined register names .const r0 r1 r2 r3 r4 ra rv sp ; Segment defs, Harvard model (defaults were ok too) .segment .text 16 0x10000 0 .VMEM .segment .data 16 0x10000 0 .VMEM

And here's the Verilog code itself. Notice that VMEM 0 is used to initialize the reciprocal lookup table -- it needs to be there. The Harvard-style separate memories for instructions and data should normally be initialized to hold your test program, but here I've just explicitly intinialized a few registers and placed a few instructions in the instruction memory. This is a pretty sad test, and certainly not how you were supposed to test your code... but I want you to be working that out for yourselves. In fact, I don't promise this code is 100% correct, because I've semi-deliberately done very little testing of it. I don't want you blindly copying what I do: you can and should do better just using this as a starting point. ;-)

Verilog source code:

// Barely-tested multi-cycle TACKY sample solution // Written by Henry Dietz, http://aggregate.org/hankd // basic sizes of things `define WORD [15:0] `define TAGWORD [16:0] `define OP [4:0] `define STATE [4:0] // some state numbers are OPs `define REGSIZE [7:0] `define MEMSIZE [65535:0] // field placements and values `define TAG [16] // type tag in registers `define Op0 [15:11] // opcode field `define Reg0 [10:8] // register number field `define Op1 [7:3] // second opcode `define Reg1 [2:0] // second register number, also size `define Imm8 [7:0] // also used as size `define OpPack [15:14] // if not 2'b11, packed inst // TACKY data type flag values `define TFLOAT 1'b1 `define TINT 1'b0 // opcode values, also state numbers `define OPa2r 5'b00000 `define OPr2a 5'b00001 `define OPadd 5'b00010 `define OPand 5'b00011 `define OPcvt 5'b00100 `define OPdiv 5'b00101 `define OPmul 5'b00110 `define OPnot 5'b00111 `define OPor 5'b01000 `define OPsh 5'b01001 `define OPslt 5'b01010 `define OPsub 5'b01011 `define OPxor 5'b01100 `define OPjr 5'b10000 `define OPlf 5'b10001 `define OPli 5'b10010 `define OPst 5'b10011 `define OPcf8 5'b11000 `define OPci8 5'b11001 `define OPjnz8 5'b11010 `define OPjz8 5'b11011 `define OPjp8 5'b11100 `define OPpre 5'b11101 `define OPsys 5'b11110 // state numbers `define Start `OPa2r `define Decode `OPr2a `define Pack0 `OPadd `define Pack1 `OPand // Floating point Verilog modules for CPE480 // Created February 19, 2019 by Henry Dietz, http://aggregate.org/hankd // Distributed under CC BY 4.0, https://creativecommons.org/licenses/by/4.0/ // Field definitions `define WORD [15:0] // generic machine word size `define INT signed [15:0] // integer size `define FLOAT [15:0] // half-precision float size `define FSIGN [15] // sign bit `define FEXP [14:7] // exponent `define FFRAC [6:0] // fractional part (leading 1 implied) // Constants `define FZERO 16'b0 // float 0 `define F32767 16'h46ff // closest approx to 32767, actually 32640 `define F32768 16'hc700 // -32768 // Count leading zeros, 16-bit (5-bit result) d=lead0s(s) module lead0s(d, s); output wire [4:0] d; input wire `WORD s; wire [4:0] t; wire [7:0] s8; wire [3:0] s4; wire [1:0] s2; assign t[4] = 0; assign {t[3],s8} = ((|s[15:8]) ? {1'b0,s[15:8]} : {1'b1,s[7:0]}); assign {t[2],s4} = ((|s8[7:4]) ? {1'b0,s8[7:4]} : {1'b1,s8[3:0]}); assign {t[1],s2} = ((|s4[3:2]) ? {1'b0,s4[3:2]} : {1'b1,s4[1:0]}); assign t[0] = !s2[1]; assign d = (s ? t : 16); endmodule // Float set-less-than, 16-bit (1-bit result) torf=a<b module fslt(torf, a, b); output wire torf; input wire `FLOAT a, b; assign torf = (a `FSIGN && !(b `FSIGN)) || (a `FSIGN && b `FSIGN && (a[14:0] > b[14:0])) || (!(a `FSIGN) && !(b `FSIGN) && (a[14:0] < b[14:0])); endmodule // Floating-point addition, 16-bit r=a+b module fadd(r, a, b); output wire `FLOAT r; input wire `FLOAT a, b; wire `FLOAT s; wire [8:0] sexp, sman, sfrac; wire [7:0] texp, taman, tbman; wire [4:0] slead; wire ssign, aegt, amgt, eqsgn; assign r = ((a == 0) ? b : ((b == 0) ? a : s)); assign aegt = (a `FEXP > b `FEXP); assign texp = (aegt ? (a `FEXP) : (b `FEXP)); assign taman = (aegt ? {1'b1, (a `FFRAC)} : ({1'b1, (a `FFRAC)} >> (texp - a `FEXP))); assign tbman = (aegt ? ({1'b1, (b `FFRAC)} >> (texp - b `FEXP)) : {1'b1, (b `FFRAC)}); assign eqsgn = (a `FSIGN == b `FSIGN); assign amgt = (taman > tbman); assign sman = (eqsgn ? (taman + tbman) : (amgt ? (taman - tbman) : (tbman - taman))); lead0s m0(slead, {sman, 7'b0}); assign ssign = (amgt ? (a `FSIGN) : (b `FSIGN)); assign sfrac = sman << slead; assign sexp = (texp + 1) - slead; assign s = (sman ? (sexp ? {ssign, sexp[7:0], sfrac[7:1]} : 0) : 0); endmodule // Floating-point multiply, 16-bit r=a*b module fmul(r, a, b); output wire `FLOAT r; input wire `FLOAT a, b; wire [15:0] m; // double the bits in a fraction, we need high bits wire [7:0] e; wire s; assign s = (a `FSIGN ^ b `FSIGN); assign m = ({1'b1, (a `FFRAC)} * {1'b1, (b `FFRAC)}); assign e = (((a `FEXP) + (b `FEXP)) -127 + m[15]); assign r = (((a == 0) || (b == 0)) ? 0 : (m[15] ? {s, e, m[14:8]} : {s, e, m[13:7]})); endmodule // Floating-point reciprocal, 16-bit r=1.0/a // Note: requires initialized inverse fraction lookup table module frecip(r, a); output wire `FLOAT r; input wire `FLOAT a; reg [6:0] look[127:0]; initial $readmemh0(look); assign r `FSIGN = a `FSIGN; assign r `FEXP = 253 + (!(a `FFRAC)) - a `FEXP; assign r `FFRAC = look[a `FFRAC]; endmodule // Floating-point shift, 16 bit // Shift +left,-right by integer module fshift(r, f, i); output wire `FLOAT r; input wire `FLOAT f; input wire `INT i; assign r `FFRAC = f `FFRAC; assign r `FSIGN = f `FSIGN; assign r `FEXP = (f ? (f `FEXP + i) : 0); endmodule // Integer to float conversion, 16 bit module i2f(f, i); output wire `FLOAT f; input wire `INT i; wire [4:0] lead; wire `WORD pos; assign pos = (i[15] ? (-i) : i); lead0s m0(lead, pos); assign f `FFRAC = (i ? ({pos, 8'b0} >> (16 - lead)) : 0); assign f `FSIGN = i[15]; assign f `FEXP = (i ? (128 + (14 - lead)) : 0); endmodule // Float to integer conversion, 16 bit // Note: out-of-range values go to -32768 or 32767 module f2i(i, f); output wire `INT i; input wire `FLOAT f; wire `FLOAT ui; wire tiny, big; fslt m0(tiny, f, `F32768); fslt m1(big, `F32767, f); assign ui = {1'b1, f `FFRAC, 16'b0} >> ((128+22) - f `FEXP); assign i = (tiny ? 0 : (big ? 32767 : (f `FSIGN ? (-ui) : ui))); endmodule // End of float library module alu(valid, o, op, a, b); output valid; output `TAGWORD o; input `OP op; input `TAGWORD a, b; reg `TAGWORD t; reg ok; wire sltf; wire `WORD cvi; wire `FLOAT addf, cvf, recipf, mulf, shf; wire signed `WORD sa, sb; fadd myfadd(addf, a `WORD, ((op == `OPsub) ? (b `WORD ^ 16'h8000) : b `WORD)); i2f myi2f(cvf, b `WORD); f2i myf2i(cvi, b `WORD); frecip myfrecip(recipf, b `WORD); fmul myfmul(mulf, a `WORD, ((op == `OPmul) ? b `WORD : recipf)); fshift myfshift(shf, a `WORD, b `WORD); fslt myfslt(sltf, a `WORD, b `WORD); assign sa = a `WORD; // signed version of a assign sb = b `WORD; // signed version of b assign o = t; assign valid = ok; always @* begin t = a; ok = 1; case ({a `TAG, op}) {`TINT, `OPr2a}, {`TFLOAT, `OPr2a}: t = b; {`TINT, `OPadd}: t = {`TINT, (a `WORD + b `WORD)}; {`TFLOAT, `OPadd}: t = {`TFLOAT, addf}; {`TINT, `OPand}, {`TFLOAT, `OPand}: t `WORD = a `WORD & b `WORD; {`TINT, `OPcvt}, {`TFLOAT, `OPcvt}: t = ((b `TAG == `TFLOAT) ? {`TINT, cvi} : {`TFLOAT, cvf}); {`TINT, `OPdiv}: t = {`TINT, (a `WORD / b `WORD)}; {`TFLOAT, `OPdiv}: t = {`TFLOAT, mulf}; {`TINT, `OPmul}: t = {`TINT, (a `WORD * b `WORD)}; {`TFLOAT, `OPmul}: t = {`TFLOAT, mulf}; {`TINT, `OPnot}, {`TFLOAT, `OPnot}: t `WORD = ~(b `WORD); {`TINT, `OPor}, {`TFLOAT, `OPor}: t `WORD = (a `WORD | b `WORD); {`TINT, `OPsh}: t = {`TINT, ((sb < 0) ? (sa >> -sb) : (sa << sb))}; {`TFLOAT, `OPsh}: t = {`TFLOAT, shf}; {`TINT, `OPslt}: t = {`TINT, (sa < sb)}; {`TFLOAT, `OPslt}: t = {`TINT, 15'b0, sltf}; {`TINT, `OPsub}: t `WORD = sa - sb; {`TFLOAT, `OPsub}: t = {`TFLOAT, addf}; {`TINT, `OPxor}, {`TFLOAT, `OPxor}: t `WORD = (a `WORD ^ b `WORD); default: ok = 0; endcase end endmodule module processor(halt, reset, clk); output reg halt; input reset, clk; reg `TAGWORD r `REGSIZE; wire `TAGWORD aluv; reg `WORD text `MEMSIZE; // instruction memory reg `WORD data `MEMSIZE; // data memory reg `WORD pc = 0; reg `WORD ir; reg `Imm8 pre, sys; reg `STATE s, op; reg `Reg1 rn; wire valid; alu myalu(valid, aluv, op, r[s == `Pack1], r[rn]); always @(posedge reset) begin halt <= 0; pc <= 0; s <= `Start; // initialize some stuff... r[0] = 17'h00001; // 1 r[1] = 17'h13f80; // 1.0 r[2] = 17'h00002; // 2 r[3] = 17'h14000; // 2.0 text[0] = { `OPadd, 3'd2, `OPadd, 3'd3 }; // r[0] = 17'h00003, r[1] = 17'h14040 text[1] = { `OPsub, 3'd2, `OPsub, 3'd3 }; text[2] = { `OPsys, 3'd0, 8'd0 }; // the better way would be using readmem... // readmemh1(text); // readmemh2(data); end always @(posedge clk) begin case (s) `Start: begin ir <= text[pc]; s <= `Decode; end `Decode: begin pc <= pc + 1; op <= ir `Op0; rn <= ir `Reg0; s <= ((ir `OpPack == 2'b11) ? ir `Op0 : `Pack0); end `OPcf8: begin r[rn] <= {`TFLOAT, pre, ir `Imm8}; s <= `Start; end `OPci8: begin r[rn] <= {`TINT, pre, ir `Imm8}; s <= `Start; end `OPjnz8: begin if (r[rn] `WORD) pc <= {pre, ir `Imm8}; s <= `Start; end `OPjz8: begin if (!r[rn] `WORD) pc <= {pre, ir `Imm8}; s <= `Start; end `OPjp8: begin pc <= {pre, ir `Imm8}; s <= `Start; end `OPpre: begin pre <= ir `Imm8; s <= `Start; end `Pack0: begin case (op) `OPjr: pc <= r[rn] `WORD; `OPlf: r[rn] <= {`TFLOAT, data[r[0] `WORD]}; `OPli: r[rn] <= {`TINT, data[r[0] `WORD]}; `OPst: data[r[rn]] <= r[0] `WORD; `OPa2r: r[rn] <= r[0]; default: if (valid) r[0] <= aluv; endcase op <= ir `Op1; rn <= ir `Reg1; s <= `Pack1; end `Pack1: begin case (ir `Op1) `OPjr: pc <= r[rn] `WORD; `OPlf: r[rn] <= {`TFLOAT, data[r[1] `WORD]}; `OPli: r[rn] <= {`TINT, data[r[1] `WORD]}; `OPst: data[r[rn]] <= r[1] `WORD; `OPa2r: r[rn] <= r[1]; default: if (valid) r[1] <= aluv; endcase s <= `Start; end // default is OPsys and some illegal instructions default: begin sys <= ir `Imm8; halt <= 1; end endcase end endmodule module testbench; reg reset = 0; reg clk = 0; wire halted; processor PE(halted, reset, clk); initial begin $dumpfile; $dumpvars(1, PE.pc, PE.r[0], PE.r[1]); // would normally trace 0, PE #10 reset = 1; #10 reset = 0; while (!halted) begin #10 clk = 1; #10 clk = 0; end $finish; end endmodule

VMEM file contents:

VMEM 0:
// Reciprocal fraction // lookup table, as VMEM @0000 00 7e 7c 7a 78 76 74 72 70 6f 6d 6b 6a 68 66 65 63 61 60 5e 5d 5b 5a 59 57 56 54 53 52 50 4f 4e 4c 4b 4a 49 47 46 45 44 43 41 40 3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30 2f 2e 2d 2c 2b 2a 29 28 28 27 26 25 24 23 23 22 21 20 1f 1f 1e 1d 1c 1c 1b 1a 19 19 18 17 17 16 15 14 14 13 12 12 11 10 10 0f 0f 0e 0d 0d 0c 0c 0b 0a 0a 09 09 08 07 07 06 06 05 05 04 04 03 03 02 02 01 01 00

The C program that generated this page was written by Hank Dietz using the CGIC library to implement the CGI interface.

Advanced Computer Architecture.