LARs (and CRegs)

Line Associative Registers (LARs) are the basis for a new class of processor architectures in which memory accesses are minimized by explicitly managing wide lines of instructions and data in processor registers. They can be viewed as a sort of synthesis between our earlier work on SIMD Within A Register (SWAR) and on Cache-Registers (CRegs). The following publications explain some of the key concepts....

Publications On LARs

The following are publications directly about LARs:

Publications On CRegs

Professor Dietz's 1987 Ph.D. work centered on compiler and language mechanisms for dealing with aliases... so it was not much of a stretch to start thinking in terms of architectural mechanisms to help with the same type of problems. The concept of CRegs also dates from 1987.... The following are publications directly about CRegs.

Related Publications

The following are publications on related topics:

The Aggregate. The only thing set in stone is our name.